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2024-11-22 - 10:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Fri Nov 22, 2024 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
492299709701,7cyclictest4927-21kerneloops21:38:523
490899709700,7cyclictest4927-21kerneloops00:18:201
490899707700,5cyclictest4927-21kerneloops20:44:311
490899706698,6cyclictest4927-21kerneloops22:42:071
492299705696,7cyclictest4927-21kerneloops21:29:293
491599705698,5cyclictest4927-21kerneloops23:40:542
490899705702,2cyclictest4927-21kerneloops22:57:241
490899705697,6cyclictest4927-21kerneloops20:55:491
490899705696,7cyclictest4927-21kerneloops21:47:501
490099705698,5cyclictest4927-21kerneloops20:05:240
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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