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2024-07-16 - 08:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Mon Jul 15, 2024 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
364399679670,7cyclictest4927-21kerneloops11:15:080
365699672661,9cyclictest4927-21kerneloops11:19:562
364399662658,2cyclictest4927-21kerneloops11:08:440
365699661652,7cyclictest4927-21kerneloops11:38:252
364899659651,6cyclictest4927-21kerneloops10:06:341
366499658652,5cyclictest4927-21kerneloops09:03:493
366499656649,5cyclictest4927-21kerneloops08:29:233
365699656649,5cyclictest4927-21kerneloops07:26:572
365699656648,6cyclictest4927-21kerneloops10:11:222
364899656650,4cyclictest4927-21kerneloops09:24:501
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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