You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2024-07-16 - 08:14
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot7.osadl.org (updated Mon Jul 15, 2024 12:44:20)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
"interval":200,4564
"cycles":100000000,4563
"load":"idle",4562
"condition":{4561
"clock":"2300"4559
"family":"x86",4558
"vendor":"Intel",4557
"processor":{4555
"dataset":"2024-01-08T15:37:35+0100"4553
"origin":"2024-01-08T12:43:22+0100",4552
"timestamps":{4551
"granularity":"microseconds"4549
7320:41:044547
80,20:41:114546
"maxima":[4545
020:39:514542
0,20:39:514541
0,20:39:514540
0,20:39:514539
0,20:39:514538
0,20:39:514537
0,20:39:514536
0,20:39:514535
0,20:39:514534
0,20:39:514533
0,20:39:514532
0,20:39:514531
0,20:39:514530
0,20:39:514529
0,20:39:514528
0,20:39:514527
0,20:39:514526
0,20:39:514525
0,20:39:514524
0,20:39:514523
0,20:39:514522
0,20:39:514521
0,20:39:514520
0,20:39:514519
0,20:39:514518
0,20:39:514517
0,20:39:514516
0,20:39:514515
0,20:39:514514
0,20:39:514513
0,20:39:514512
0,20:39:514511
0,20:39:514510
0,20:39:514509
0,20:39:514508
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional