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2024-11-22 - 16:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Fri Nov 22, 2024 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
155479910734753449,53802cyclictest3314-21ssh12:15:070
155479910692853462,53466cyclictest0-21swapper10:01:490
155479910674053452,53225cyclictest3950irq/9-acpi11:28:230
155479910670753466,53241cyclictest0-21swapper11:38:360
155479910668353421,53170cyclictest0-21swapper08:05:050
155479910665853463,53100cyclictest32708-21diskmemload11:02:460
155479910665553393,53171cyclictest0-21swapper07:54:420
155479910655953478,53081cyclictest0-21swapper10:12:010
155479910655453475,53079cyclictest0-21swapper08:47:070
155479910655053391,53094cyclictest0-21swapper10:56:540
155479910649153406,53085cyclictest0-21swapper10:15:020
155479910648053475,53005cyclictest0-21swapper09:22:470
155479910642253388,53034cyclictest0-21swapper07:35:360
155479910637753128,53246cyclictest0-21swapper09:34:010
155479910630253390,52846cyclictest0-21swapper07:30:050
155479910628153386,52804cyclictest0-21swapper07:24:130
155479910623153440,52791cyclictest0-21swapper08:43:060
155479910623153385,52803cyclictest0-21swapper12:06:040
155479910622353436,52787cyclictest0-21swapper08:16:580
155479910621153415,52796cyclictest0-21swapper09:29:090
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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