You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-04-02 - 08:27
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Wed Apr 02, 2025 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
240469910736053397,53843cyclictest3816-21diskmemload22:42:270
240469910692553444,53359cyclictest3816-21diskmemload21:57:540
240469910663153388,53178cyclictest0-21swapper20:18:050
240469910658053392,53096cyclictest0-21swapper00:19:450
240469910654953389,53095cyclictest0-21swapper20:42:320
240469910651153473,53038cyclictest0-21swapper22:35:450
240469910649953472,53027cyclictest0-21swapper00:08:120
240469910648353454,53029cyclictest0-21swapper23:52:370
240469910648253422,53060cyclictest0-21swapper23:17:570
240469910644253444,52998cyclictest0-21swapper22:13:390
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional