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2024-07-16 - 08:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot5.osadl.org (updated Mon Jul 15, 2024 12:43:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3272899113916020,5368cyclictest20043-21kworker/0:109:26:390
3272899106165430,5182cyclictest20043-21kworker/0:109:23:260
3272899102445358,4883cyclictest10952-21kworker/0:008:59:550
3272899102295448,4778cyclictest2550-21kworker/0:009:41:070
3272899100235032,4979cyclictest2550-21kworker/0:010:59:580
327289999135154,4748cyclictest5705-21kworker/0:112:36:140
327289996534847,4795cyclictest11270-21kworker/0:211:59:300
327289996505133,4507cyclictest27566-21kworker/0:011:14:220
327289996305139,4488cyclictest10952-21kworker/0:007:40:220
327289995764961,4555cyclictest10952-21kworker/0:009:13:320
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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