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2025-04-02 - 08:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot5.osadl.org (updated Wed Apr 02, 2025 00:43:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
168129998445250,4589cyclictest12577-21kworker/0:220:55:560
168129998335143,4686cyclictest12577-21kworker/0:221:23:450
168129997755214,4556cyclictest12577-21kworker/0:220:40:400
168129996575051,4595cyclictest12577-21kworker/0:221:40:170
168129993724670,4642cyclictest26710-21kworker/0:019:22:360
168129991324590,4527cyclictest12577-21kworker/0:222:04:000
168129991034587,4511cyclictest12577-21kworker/0:221:35:440
168129990934685,4397cyclictest926-21kworker/0:023:31:300
168129990884682,4395cyclictest13284-21kworker/0:022:58:440
168129990684569,4494cyclictest24325-21kworker/0:223:07:110
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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