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2024-11-22 - 10:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot5.osadl.org (updated Fri Nov 22, 2024 00:43:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
257399116686021,5636cyclictest19949-21kworker/0:121:16:480
257399113425971,5367cyclictest25558-21kworker/0:120:19:130
257399105415544,4955cyclictest23814-21kworker/0:023:33:030
257399102355330,4894cyclictest16691-21kworker/0:022:08:050
257399102275221,4995cyclictest23814-21kworker/0:023:22:160
25739996705118,4541cyclictest25558-21kworker/0:120:35:340
25739993894806,4572cyclictest25558-21kworker/0:120:48:020
25739993484784,4553cyclictest19949-21kworker/0:122:03:460
25739993334782,4540cyclictest19949-21kworker/0:121:33:440
25739992594743,4505cyclictest4281-21kworker/0:123:46:410
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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