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2024-11-22 - 08:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by a total of 26594 SMIs that occured during the measurement.
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 376 highest latencies:
System rack6slot4.osadl.org (updated Fri Nov 22, 2024 01:09:11)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
"interval":200,6448
"cycles":100000000,6447
"load":"idle",6446
"condition":{6445
"clock":"1100"6443
"family":"x86",6442
"vendor":"Intel",6441
"processor":{6439
"dataset":"2024-01-08T03:36:49+01:00"6437
"origin":"2024-01-08T00:43:22+01:00",6436
"timestamps":{6435
"granularity":"microseconds"6433
32412:13:556431
331,12:08:316430
"maxima":[6429
012:08:316426
0,12:08:316425
0,12:08:316424
0,12:08:316423
0,12:08:316422
0,12:08:316421
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0,12:08:316409
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1,12:08:316351
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1,12:08:316348
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1,12:08:316344
2,12:08:316343
1,12:08:316342
3,12:08:316341
0,12:08:316340
0,12:08:316339
4,12:08:316338
0,12:08:316337
2,12:08:316336
3,12:08:316335
7,12:08:316334
5,12:08:316333
7,12:08:316332
7,12:08:316331
6,12:08:316330
2,12:08:316329
4,12:08:316328
1,12:08:316327
3,12:08:316326
1,12:08:316325
3,12:08:316324
4,12:08:316323
8,12:08:316322
5,12:08:316321
5,12:08:316320
6,12:08:316319
13,12:08:316318
4,12:08:316317
14,12:08:316316
16,12:08:316315
10,12:08:316314
14,12:08:316313
12,12:08:316312
17,12:08:316311
16,12:08:316310
14,12:08:316309
18,12:08:316308
12,12:08:316307
21,12:08:316306
21,12:08:316305
27,12:08:316304
24,12:08:316303
28,12:08:316302
31,12:08:316301
26,12:08:316300
26,12:08:316299
31,12:08:316298
18,12:08:316297
32,12:08:316296
40,12:08:316295
24,12:08:316294
43,12:08:316293
25,12:08:316292
34,12:08:316291
41,12:08:316290
33,12:08:316289
40,12:08:316288
44,12:08:316287
49,12:08:316286
58,12:08:316285
51,12:08:316284
48,12:08:316283
57,12:08:316282
69,12:08:316281
83,12:08:316280
81,12:08:316279
74,12:08:316278
75,12:08:316277
98,12:08:316276
101,12:08:316275
105,12:08:316274
122,12:08:316273
137,12:08:316272
145,12:08:316271
143,12:08:316270
139,12:08:316269
177,12:08:316268
183,12:08:316267
200,12:08:316266
228,12:08:316265
243,12:08:316264
286,12:08:316263
299,12:08:316262
305,12:08:316261
325,12:08:316260
334,12:08:316259
327,12:08:316258
327,12:08:316257
355,12:08:316256
401,12:08:316255
407,12:08:316254
405,12:08:316253
438,12:08:316252
434,12:08:316251
409,12:08:316250
406,12:08:316249
367,12:08:316248
286,12:08:316247
266,12:08:316246
226,12:08:316245
204,12:08:316244
180,12:08:316243
188,12:08:316242
197,12:08:316241
220,12:08:316240
215,12:08:316239
237,12:08:316238
255,12:08:316237
257,12:08:316236
233,12:08:316235
162,12:08:316234
99,12:08:316233
105,12:08:316232
46,12:08:316231
43,12:08:316230
12,12:08:316229
8,12:08:316228
2,12:08:316227
6,12:08:316226
3,12:08:316225
5,12:08:316224
3,12:08:316223
3,12:08:316222
5,12:08:316221
2,12:08:316220
4,12:08:316219
3,12:08:316218
7,12:08:316217
15,12:08:316216
13,12:08:316215
15,12:08:316214
5,12:08:316213
12,12:08:316212
8,12:08:316211
6,12:08:316210
3,12:08:316209
3,12:08:316208
2,12:08:316207
2,12:08:316206
2,12:08:316205
1,12:08:316204
3,12:08:316203
1,12:08:316202
4,12:08:316201
2,12:08:316200
0,12:08:316199
3,12:08:316198
0,12:08:316197
3,12:08:316196
3,12:08:316195
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3,12:08:316191
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2,12:08:316189
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2,12:08:316186
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3,12:08:316175
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0,12:08:316153
4,12:08:316152
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1,12:08:316069
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4,12:08:316067
8,12:08:316066
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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