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2024-11-21 - 16:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by a total of 26600 SMIs that occured during the measurement.
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot4.osadl.org (updated Thu Nov 21, 2024 13:09:11)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
"interval":200,6448
"cycles":100000000,6447
"load":"idle",6446
"condition":{6445
"clock":"1100"6443
"family":"x86",6442
"vendor":"Intel",6441
"processor":{6439
"dataset":"2024-01-08T03:36:49+01:00"6437
"origin":"2024-01-08T00:43:22+01:00",6436
"timestamps":{6435
"granularity":"microseconds"6433
32412:13:556431
331,12:08:316430
"maxima":[6429
012:08:316426
0,12:08:316425
0,12:08:316424
0,12:08:316423
0,12:08:316422
0,12:08:316421
0,12:08:316420
0,12:08:316419
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0,12:08:316413
0,12:08:316412
0,12:08:316411
0,12:08:316410
0,12:08:316409
0,12:08:316408
0,12:08:316407
0,12:08:316406
0,12:08:316405
0,12:08:316404
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0,12:08:316402
0,12:08:316401
0,12:08:316400
0,12:08:316399
0,12:08:316398
0,12:08:316397
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0,12:08:316393
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0,12:08:316385
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0,12:08:316381
0,12:08:316380
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0,12:08:316364
0,12:08:316363
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1,12:08:316351
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1,12:08:316348
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1,12:08:316346
0,12:08:316345
1,12:08:316344
2,12:08:316343
1,12:08:316342
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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