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2024-12-26 - 15:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Thu Dec 26, 2024 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
18662830,0sleep01868-22cpuspeed11:28:390
2718324912,8sleep00-21swapper/007:05:460
27509994131,1cyclictest245950irq/16-enp2s0f010:38:460
27509994031,1cyclictest245950irq/16-enp2s0f010:13:460
27509994031,1cyclictest245950irq/16-enp2s0f009:03:460
27509994031,1cyclictest245950irq/16-enp2s0f008:53:440
27509993932,6cyclictest245950irq/16-enp2s0f008:23:460
27509993932,0cyclictest245950irq/16-enp2s0f010:28:440
27509993931,1cyclictest245950irq/16-enp2s0f008:38:500
27509993931,1cyclictest245950irq/16-enp2s0f007:43:530
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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