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2025-04-02 - 08:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot2.osadl.org (updated Wed Apr 02, 2025 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2354024512,25sleep00-21swapper/019:05:290
2371999420,1cyclictest245950irq/16-enp2s0f021:16:580
234882388,8sleep10-21swapper/119:04:561
23719993527,7cyclictest245950irq/16-enp2s0f019:21:570
23720993433,0cyclictest167950irq/16-i91521:30:501
23720993432,1cyclictest167950irq/16-i91523:24:041
23720993432,1cyclictest167950irq/16-i91523:12:111
23720993432,1cyclictest167950irq/16-i91522:56:551
23720993432,1cyclictest167950irq/16-i91522:09:551
23719993434,0cyclictest245950irq/16-enp2s0f021:02:460
23719993434,0cyclictest245950irq/16-enp2s0f000:24:400
23719993433,0cyclictest245950irq/16-enp2s0f023:08:270
23719993433,0cyclictest245950irq/16-enp2s0f019:43:470
23719993432,1cyclictest245950irq/16-enp2s0f022:16:580
23719993432,1cyclictest245950irq/16-enp2s0f021:56:530
23719993432,1cyclictest245950irq/16-enp2s0f020:12:010
23719993432,1cyclictest245950irq/16-enp2s0f019:57:030
23719993432,1cyclictest245950irq/16-enp2s0f019:11:590
23719993432,1cyclictest245950irq/16-enp2s0f000:06:520
23720993333,0cyclictest167950irq/16-i91519:45:161
23720993332,0cyclictest245950irq/16-enp2s0f023:52:181
23720993332,0cyclictest245950irq/16-enp2s0f022:24:001
23720993332,0cyclictest245950irq/16-enp2s0f021:40:251
23720993332,0cyclictest245950irq/16-enp2s0f021:36:141
23720993332,0cyclictest245950irq/16-enp2s0f020:39:041
23720993332,0cyclictest245950irq/16-enp2s0f020:31:591
23720993332,0cyclictest245950irq/16-enp2s0f019:21:541
23720993332,0cyclictest167950irq/16-i91523:47:591
23720993332,0cyclictest167950irq/16-i91523:40:561
23720993332,0cyclictest167950irq/16-i91523:07:221
23720993332,0cyclictest167950irq/16-i91522:52:021
23720993332,0cyclictest167950irq/16-i91522:47:041
23720993332,0cyclictest167950irq/16-i91522:43:041
23720993332,0cyclictest167950irq/16-i91521:45:121
23720993332,0cyclictest167950irq/16-i91521:11:561
23720993332,0cyclictest167950irq/16-i91521:08:051
23720993332,0cyclictest167950irq/16-i91519:51:531
23720993331,1cyclictest167950irq/16-i91522:32:001
23720993331,1cyclictest167950irq/16-i91521:52:041
23720993331,1cyclictest167950irq/16-i91520:53:431
23720993331,1cyclictest167950irq/16-i91520:06:511
23720993331,1cyclictest167950irq/16-i91500:16:551
23719993332,0cyclictest245950irq/16-enp2s0f023:56:570
23719993332,0cyclictest245950irq/16-enp2s0f023:43:110
23719993332,0cyclictest245950irq/16-enp2s0f023:31:580
23719993332,0cyclictest245950irq/16-enp2s0f023:26:490
23719993332,0cyclictest245950irq/16-enp2s0f023:16:580
23719993332,0cyclictest245950irq/16-enp2s0f023:11:570
23719993332,0cyclictest245950irq/16-enp2s0f022:56:560
23719993332,0cyclictest245950irq/16-enp2s0f022:51:550
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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