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2024-11-22 - 10:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Fri Nov 22, 2024 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
226952479,8sleep00-21swapper/019:05:510
229242438,8sleep10-21swapper/119:08:101
161842410,0sleep016187-22grep00:14:280
23085994032,7cyclictest245950irq/16-enp2s0f023:24:250
23085993433,0cyclictest245950irq/16-enp2s0f023:54:290
23085993432,1cyclictest245950irq/16-enp2s0f023:04:240
23085993432,1cyclictest245950irq/16-enp2s0f022:57:350
23085993432,1cyclictest245950irq/16-enp2s0f022:34:300
23085993432,1cyclictest245950irq/16-enp2s0f022:10:070
23085993432,1cyclictest245950irq/16-enp2s0f021:50:440
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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