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2025-04-02 - 08:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Wed Apr 02, 2025 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2354024512,25sleep00-21swapper/019:05:290
2371999420,1cyclictest245950irq/16-enp2s0f021:16:580
234882388,8sleep10-21swapper/119:04:561
23719993527,7cyclictest245950irq/16-enp2s0f019:21:570
23720993433,0cyclictest167950irq/16-i91521:30:501
23720993432,1cyclictest167950irq/16-i91523:24:041
23720993432,1cyclictest167950irq/16-i91523:12:111
23720993432,1cyclictest167950irq/16-i91522:56:551
23720993432,1cyclictest167950irq/16-i91522:09:551
23719993434,0cyclictest245950irq/16-enp2s0f021:02:460
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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