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2025-04-02 - 04:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Wed Apr 02, 2025 01:00:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3858699292260,10cyclictest15984-21CPU1
3858699267263,2cyclictest0-21swapper/119:14:191
3858699267263,2cyclictest0-21swapper/119:14:191
3858699219206,10cyclictest15984-21CPU1
3858699219206,10cyclictest15984-21CPU1
3858699219202,8cyclictest33915-21NetworkChangeNo20:00:201
3858699219202,8cyclictest33915-21NetworkChangeNo20:00:201
38617992138,178cyclictest0-21swapper/2619:30:2119
3858699213200,7cyclictest0-21swapper/122:35:191
3858699213200,7cyclictest0-21swapper/122:35:191
3858699207186,13cyclictest37930-21sshd21:15:181
3858699207186,13cyclictest37930-21sshd21:15:181
3858699207186,13cyclictest37930-21sshd21:15:181
3860599200195,3cyclictest0-21swapper/1522:55:227
3860599200195,3cyclictest0-21swapper/1522:55:217
3860599200195,3cyclictest0-21swapper/1522:55:217
38600992002,78cyclictest4906-21CPU2
38600992002,78cyclictest4906-21CPU2
3858699198187,8cyclictest0-21swapper/100:03:001
3858699198187,8cyclictest0-21swapper/100:03:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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