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2024-11-22 - 16:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Fri Nov 22, 2024 13:01:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
356599928230,234cyclictest0-21swapper/3712:10:2231
356599928230,234cyclictest0-21swapper/3712:10:2231
35659992799,250cyclictest0-21swapper/3711:40:1831
35659992799,250cyclictest0-21swapper/3711:40:1831
356599923822,208cyclictest0-21swapper/3710:35:1431
356599923822,208cyclictest0-21swapper/3710:35:1431
356599923822,208cyclictest0-21swapper/3710:35:1431
3565799223190,27cyclictest0-21swapper/3609:12:5730
3565799223190,27cyclictest0-21swapper/3609:12:5730
3565799223190,27cyclictest0-21swapper/3609:12:5730
356599922228,175cyclictest23458-21inotify_reader07:10:1631
356599922228,175cyclictest23458-21inotify_reader07:10:1631
356599920818,184cyclictest0-21swapper/3711:45:1531
356599920818,184cyclictest0-21swapper/3711:45:1431
356599920818,184cyclictest0-21swapper/3711:45:1431
356489920720,183cyclictest10880-21inotify_reader09:10:1822
356489920720,183cyclictest10880-21inotify_reader09:10:1822
356489920720,183cyclictest10880-21inotify_reader09:10:1822
35631992041,199cyclictest0-21swapper/1408:00:186
35631992041,199cyclictest0-21swapper/1408:00:186
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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