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2024-07-16 - 08:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Mon Jul 15, 2024 13:00:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1591899264241,21cyclictest0-21swapper/912:12:5639
1591899264241,21cyclictest0-21swapper/912:12:5639
159159922713,119cyclictest0-21swapper/609:44:5836
159159922713,119cyclictest0-21swapper/609:44:5836
1594299223219,2cyclictest0-21swapper/3009:10:2024
1594299223219,2cyclictest0-21swapper/3009:10:1924
1594599217164,32cyclictest2687-21lxd09:44:5926
1594599217164,32cyclictest2687-21lxd09:44:5926
1591799212206,4cyclictest0-21swapper/811:40:4838
1591799212206,4cyclictest0-21swapper/811:40:4838
1591799212206,4cyclictest0-21swapper/811:40:4838
1594899206169,35cyclictest0-21swapper/3507:20:2729
1594899206169,35cyclictest0-21swapper/3507:20:2729
1595399205199,3cyclictest0-21swapper/3809:10:2732
1595399205199,3cyclictest0-21swapper/3809:10:2732
1593799204197,5cyclictest0-21swapper/2507:55:0118
1593799204194,6cyclictest0-21swapper/2508:00:0018
1591099204200,2cyclictest0-21swapper/109:10:321
1591099204200,2cyclictest0-21swapper/109:10:311
1592799200166,32cyclictest0-21swapper/1709:40:289
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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