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2024-11-22 - 10:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Fri Nov 22, 2024 01:01:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
177799260255,3cyclictest0-21swapper/1922:22:4911
177799260255,3cyclictest0-21swapper/1922:22:4811
177799237209,12cyclictest9403-21inotify_reader00:15:1811
177799237209,12cyclictest9403-21inotify_reader00:15:1811
177799231211,5cyclictest0-21swapper/1920:55:1611
177799231211,5cyclictest0-21swapper/1920:55:1511
178399225214,9cyclictest0-21swapper/2521:44:2418
178399225214,9cyclictest0-21swapper/2521:44:2418
178399225214,9cyclictest0-21swapper/2521:44:2418
1768992215,199cyclictest0-21swapper/1321:55:165
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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