You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2024-07-16 - 08:46
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack5slot4.osadl.org (updated Mon Jul 15, 2024 12:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
115662110101,6sleep00-21swapper/007:08:110
6257210899,6sleep10-21swapper/107:05:471
11554210898,7sleep30-21swapper/307:08:023
11670210797,7sleep20-21swapper/207:09:332
139462710,0sleep10-21swapper/111:45:241
243362630,0sleep20-21swapper/212:07:152
72522580,0sleep10-21swapper/109:35:301
320122580,0sleep332014-21kthreadcore09:30:273
33382560,0sleep10-21swapper/111:20:281
114152550,1sleep211423-21kthreadcore08:00:302
68092540,0sleep10-21swapper/109:53:361
243552540,0sleep30-21swapper/308:40:163
70222530,0sleep00-21swapper/012:32:540
165762530,0sleep30-21swapper/310:53:503
153572520,0sleep00-21swapper/009:58:080
1187399270,26cyclictest0-21swapper/212:28:012
1187399270,26cyclictest0-21swapper/212:28:002
1187399270,26cyclictest0-21swapper/209:45:272
1187399270,26cyclictest0-21swapper/208:55:312
1186799270,26cyclictest0-21swapper/112:27:161
1186799270,26cyclictest0-21swapper/112:27:151
1186799270,26cyclictest0-21swapper/110:45:581
1186799270,26cyclictest0-21swapper/107:43:091
1186799270,26cyclictest0-21swapper/107:21:491
1186799270,26cyclictest0-21swapper/107:18:571
1187399260,2cyclictest19975-21ssh10:19:532
1187399260,25cyclictest0-21swapper/210:13:102
1187399260,25cyclictest0-21swapper/208:51:082
1186799260,25cyclictest0-21swapper/111:04:511
1186799260,25cyclictest0-21swapper/108:49:321
1186799260,25cyclictest0-21swapper/108:06:121
1186799260,25cyclictest0-21swapper/107:35:091
11873992522,2cyclictest0-21swapper/208:30:392
11873992521,3cyclictest0-21swapper/209:07:132
1187399250,24cyclictest0-21swapper/212:20:582
1187399250,24cyclictest0-21swapper/212:15:542
1187399250,19cyclictest26231-21diskmemload11:47:062
1186799259,15cyclictest0-21swapper/112:01:291
1186799250,24cyclictest0-21swapper/111:43:231
1186799250,20cyclictest0-21swapper/108:52:551
1187399240,23cyclictest0-21swapper/211:44:432
1187399240,23cyclictest0-21swapper/210:35:302
11867992421,2cyclictest0-21swapper/107:34:101
1186799240,3cyclictest0-21swapper/110:35:141
1186799240,23cyclictest0-21swapper/112:30:361
1186799240,23cyclictest0-21swapper/107:45:581
1186799240,19cyclictest0-21swapper/109:56:131
1186599240,23cyclictest0-21swapper/012:01:090
1186599240,23cyclictest0-21swapper/011:05:240
129322317,3sleep30-21swapper/310:09:543
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional