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2024-07-16 - 08:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot4.osadl.org (updated Mon Jul 15, 2024 12:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
115662110101,6sleep00-21swapper/007:08:110
6257210899,6sleep10-21swapper/107:05:471
11554210898,7sleep30-21swapper/307:08:023
11670210797,7sleep20-21swapper/207:09:332
139462710,0sleep10-21swapper/111:45:241
243362630,0sleep20-21swapper/212:07:152
72522580,0sleep10-21swapper/109:35:301
320122580,0sleep332014-21kthreadcore09:30:273
33382560,0sleep10-21swapper/111:20:281
114152550,1sleep211423-21kthreadcore08:00:302
68092540,0sleep10-21swapper/109:53:361
243552540,0sleep30-21swapper/308:40:163
70222530,0sleep00-21swapper/012:32:540
165762530,0sleep30-21swapper/310:53:503
153572520,0sleep00-21swapper/009:58:080
1187399270,26cyclictest0-21swapper/212:28:012
1187399270,26cyclictest0-21swapper/212:28:002
1187399270,26cyclictest0-21swapper/209:45:272
1187399270,26cyclictest0-21swapper/208:55:312
1186799270,26cyclictest0-21swapper/112:27:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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