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2025-04-02 - 04:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot4.osadl.org (updated Wed Apr 02, 2025 00:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
18959213068,6sleep10-21swapper/119:09:531
1108721250,4sleep21914599cyclictest22:47:502
18784212363,7sleep00-21swapper/019:07:360
187552115104,8sleep30-21swapper/319:07:153
18863210696,7sleep20-21swapper/219:08:382
194372860,1sleep30-21swapper/323:10:143
159232730,0sleep30-21swapper/322:15:143
234102710,0sleep30-21swapper/323:30:093
79912680,0sleep30-21swapper/321:52:433
22802680,1sleep12282-21kthreadcore22:40:201
156242660,0sleep20-21swapper/200:00:002
293122650,0sleep20-21swapper/221:30:182
201072570,0sleep20-21swapper/200:20:192
233262560,0sleep10-21swapper/119:10:211
152382540,1sleep30-21swapper/323:59:413
45982490,0sleep30-21swapper/319:20:203
19143993114,16cyclictest0-21swapper/122:06:371
1914399280,27cyclictest0-21swapper/121:08:361
1914399280,27cyclictest0-21swapper/120:24:211
1914399280,26cyclictest0-21swapper/100:02:211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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