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2025-04-02 - 07:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack5slot4.osadl.org (updated Wed Apr 02, 2025 00:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
18959213068,6sleep10-21swapper/119:09:531
1108721250,4sleep21914599cyclictest22:47:502
18784212363,7sleep00-21swapper/019:07:360
187552115104,8sleep30-21swapper/319:07:153
18863210696,7sleep20-21swapper/219:08:382
194372860,1sleep30-21swapper/323:10:143
159232730,0sleep30-21swapper/322:15:143
234102710,0sleep30-21swapper/323:30:093
79912680,0sleep30-21swapper/321:52:433
22802680,1sleep12282-21kthreadcore22:40:201
156242660,0sleep20-21swapper/200:00:002
293122650,0sleep20-21swapper/221:30:182
201072570,0sleep20-21swapper/200:20:192
233262560,0sleep10-21swapper/119:10:211
152382540,1sleep30-21swapper/323:59:413
45982490,0sleep30-21swapper/319:20:203
19143993114,16cyclictest0-21swapper/122:06:371
1914399280,27cyclictest0-21swapper/121:08:361
1914399280,27cyclictest0-21swapper/120:24:211
1914399280,26cyclictest0-21swapper/100:02:211
1914399270,26cyclictest0-21swapper/123:45:281
1914399270,26cyclictest0-21swapper/123:42:271
1914399270,26cyclictest0-21swapper/123:24:531
1914399270,26cyclictest0-21swapper/122:39:531
1914399270,26cyclictest0-21swapper/122:12:101
1914399270,26cyclictest0-21swapper/121:44:401
1914399270,26cyclictest0-21swapper/120:41:121
1914399270,26cyclictest0-21swapper/120:11:591
1914399270,26cyclictest0-21swapper/119:54:421
1914399270,26cyclictest0-21swapper/119:43:391
1914399270,26cyclictest0-21swapper/119:39:181
1914399270,26cyclictest0-21swapper/100:21:241
1913899277,14cyclictest0-21swapper/021:30:340
19145992622,3cyclictest0-21swapper/219:24:322
1914599260,25cyclictest0-21swapper/221:46:092
1914599260,25cyclictest0-21swapper/221:46:092
1914599260,25cyclictest0-21swapper/220:29:502
1914399260,25cyclictest0-21swapper/122:01:341
1914399260,25cyclictest0-21swapper/121:48:281
1914399260,25cyclictest0-21swapper/121:48:281
1914399260,25cyclictest0-21swapper/121:27:241
1914399260,25cyclictest0-21swapper/120:49:211
1914399260,25cyclictest0-21swapper/119:49:391
1914399260,25cyclictest0-21swapper/100:26:461
1914399260,20cyclictest5863-21grep20:55:151
1914599250,24cyclictest15536-21ssh22:31:102
1914399250,24cyclictest0-21swapper/122:46:351
1914399250,24cyclictest0-21swapper/100:16:481
1914399250,24cyclictest0-21swapper/100:13:331
1913899250,24cyclictest0-21swapper/023:00:270
1913899250,23cyclictest0-21swapper/023:42:200
19145992422,1cyclictest0-21swapper/223:50:152
1914599242,21cyclictest0-21swapper/222:43:362
1914599242,21cyclictest0-21swapper/222:39:492
19145992420,3cyclictest0-21swapper/222:13:192
1914599241,22cyclictest0-21swapper/223:35:442
1914599240,23cyclictest0-21swapper/223:16:342
1914399246,17cyclictest0-21swapper/122:53:231
1914399240,23cyclictest0-21swapper/123:01:211
1914399240,23cyclictest0-21swapper/121:52:571
1914399240,23cyclictest0-21swapper/121:31:251
1914399240,23cyclictest0-21swapper/119:21:591
1914399240,22cyclictest0-21swapper/123:10:081
1914399240,22cyclictest0-21swapper/123:07:501
1914399240,18cyclictest0-21swapper/123:57:241
1913899240,23cyclictest0-21swapper/021:37:590
1914599233,18cyclictest28739-21ssh00:26:242
1914599232,20cyclictest0-21swapper/223:45:512
19145992321,2cyclictest0-21swapper/222:18:552
1914599231,21cyclictest0-21swapper/219:10:562
1914599230,3cyclictest0-21swapper/221:40:122
1914599230,22cyclictest0-21swapper/223:03:192
1914599230,22cyclictest0-21swapper/222:50:262
1914599230,22cyclictest0-21swapper/222:04:032
1914599230,17cyclictest0-21swapper/222:28:132
19143992322,1cyclictest211ktimersoftd/121:16:211
1914399231,21cyclictest0-21swapper/100:36:391
1914399230,23cyclictest0-21swapper/119:28:471
1914399230,22cyclictest0-21swapper/123:50:241
1914399230,22cyclictest0-21swapper/123:38:171
1914399230,22cyclictest0-21swapper/123:16:411
1914399230,22cyclictest0-21swapper/122:31:021
1914399230,22cyclictest0-21swapper/122:27:341
1914399230,22cyclictest0-21swapper/121:57:111
1914399230,22cyclictest0-21swapper/121:10:011
1914399230,17cyclictest0-21swapper/121:36:541
19138992315,7cyclictest0-21swapper/022:17:000
19138992313,9cyclictest0-21swapper/021:26:390
1913899230,22cyclictest0-21swapper/023:37:580
1913899230,22cyclictest0-21swapper/023:11:530
1913899230,22cyclictest0-21swapper/022:46:540
1913899230,22cyclictest0-21swapper/021:23:450
1914599227,14cyclictest0-21swapper/219:45:112
1914599227,13cyclictest0-21swapper/223:30:072
1914599222,19cyclictest0-21swapper/223:43:492
19145992218,3cyclictest10272-21snmpd20:02:442
1914599220,21cyclictest0-21swapper/223:25:462
1914599220,21cyclictest0-21swapper/223:13:222
1914599220,21cyclictest0-21swapper/221:50:372
1914599220,21cyclictest0-21swapper/221:36:072
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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