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2024-11-25 - 14:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack5slot4.osadl.org (updated Mon Nov 25, 2024 12:44:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
149552112102,7sleep30-21swapper/307:08:333
14775210997,7sleep20-21swapper/207:06:112
9527210899,6sleep00-21swapper/007:05:050
14990210697,6sleep10-21swapper/107:08:591
52812810,1sleep10-21swapper/111:20:161
34412710,1sleep23447-21gltestperf10:45:162
9052650,1sleep30-21swapper/312:00:193
99072590,0sleep10-21swapper/111:35:221
181622590,1sleep318165-21kthreadcore11:10:203
217602550,0sleep20-21swapper/212:24:572
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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