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2024-11-22 - 16:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot3.osadl.org (updated Fri Nov 22, 2024 12:50:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1449528451,29sleep30-21swapper/307:07:213
1442328454,26sleep50-21swapper/507:06:195
1465828249,29sleep60-21swapper/607:09:416
1442828045,30sleep10-21swapper/107:06:231
1448527945,30sleep20-21swapper/207:07:122
1464727742,30sleep40-21swapper/407:09:304
1454027643,29sleep00-21swapper/007:07:580
1454727540,30sleep70-21swapper/707:08:057
15117995251,0cyclictest0-21swapper/212:10:242
88482500,0sleep30-21swapper/312:10:173
8232500,0sleep20-21swapper/210:16:232
118812460,0sleep20-21swapper/211:24:522
32422440,0sleep00-21swapper/007:40:160
220712440,0sleep30-21swapper/310:26:333
67352430,0sleep60-21swapper/612:25:016
67352430,0sleep60-21swapper/612:25:006
15122992929,0cyclictest0-21swapper/712:10:227
15121992525,0cyclictest0-21swapper/610:05:206
15116992525,0cyclictest0-21swapper/112:10:251
15116992424,0cyclictest0-21swapper/107:10:111
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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