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2025-04-02 - 04:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot3.osadl.org (updated Wed Apr 02, 2025 00:50:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3091729186,2sleep60-21swapper/619:05:156
3091729186,2sleep60-21swapper/619:05:156
30828450,29sleep30-21swapper/319:06:163
30828450,29sleep30-21swapper/319:06:163
57728248,30sleep50-21swapper/519:09:555
57728248,30sleep50-21swapper/519:09:555
40728146,30sleep40-21swapper/419:07:374
40728146,30sleep40-21swapper/419:07:374
3043828147,30sleep20-21swapper/219:05:032
3043828147,30sleep20-21swapper/219:05:032
34428046,29sleep70-21swapper/719:06:447
34428046,29sleep70-21swapper/719:06:447
3134228075,2sleep00-21swapper/019:05:170
3134228075,2sleep00-21swapper/019:05:170
39527944,30sleep10-21swapper/119:07:261
39527944,30sleep10-21swapper/119:07:261
265822480,0sleep20-21swapper/223:48:462
88492470,0sleep70-21swapper/723:05:597
138092470,0sleep40-21swapper/422:52:194
61342440,0sleep00-21swapper/000:27:420
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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