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2025-04-02 - 08:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack5slot1.osadl.org (updated Wed Apr 02, 2025 00:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
238133911100,1EcMasterDemoSyn23819-21runintdemo5min00:24:535
238133911100,1EcMasterDemoSyn23819-21runintdemo5min00:24:525
6940391270,3EcMasterDemoSyn129899cyclictest23:03:463
21081391090,4EcMasterDemoSyn129599cyclictest20:46:510
9904391030,0EcMasterDemoSyn991029tAtEmLog_021:37:345
1665939920,0EcMasterDemoSyn1666929tAtEmLog_000:19:495
362139910,0EcMasterDemoSyn363129tAtEmLog_019:10:305
916039900,0EcMasterDemoSyn917029tAtEmLog_019:20:405
214239900,0EcMasterDemoSyn215329tAtEmLog_022:38:245
445239880,0EcMasterDemoSyn446429tAtEmLog_022:18:065
445239880,0EcMasterDemoSyn446429tAtEmLog_022:18:065
2408139880,0EcMasterDemoSyn2409129tAtEmLog_022:53:365
1003339880,0EcMasterDemoSyn1004329tAtEmLog_020:26:345
2933839870,0EcMasterDemoSyn2934829tAtEmLog_019:56:085
2082939860,0EcMasterDemoSyn2083929tAtEmLog_023:13:545
2937339850,0EcMasterDemoSyn2938329tAtEmLog_021:02:035
2658139850,0EcMasterDemoSyn2659129tAtEmLog_019:51:055
2383839840,0EcMasterDemoSyn2384829tAtEmLog_020:51:565
1586939840,0EcMasterDemoSyn1587929tAtEmLog_022:48:325
694039830,0EcMasterDemoSyn695029tAtEmLog_023:03:455
3212739830,0EcMasterDemoSyn3213729tAtEmLog_021:07:085
698339820,0EcMasterDemoSyn699329tAtEmLog_023:49:245
2052539820,0EcMasterDemoSyn2053529tAtEmLog_021:22:215
1788439820,0EcMasterDemoSyn1789429tAtEmLog_019:35:525
1528739820,0EcMasterDemoSyn1529729tAtEmLog_022:02:545
1275139820,0EcMasterDemoSyn1276129tAtEmLog_022:23:125
637939810,0EcMasterDemoSyn638929tAtEmLog_019:15:345
601439810,0EcMasterDemoSyn602429tAtEmLog_020:16:255
601439810,0EcMasterDemoSyn602429tAtEmLog_020:16:255
2108139810,0EcMasterDemoSyn2109129tAtEmLog_020:46:505
2066439810,0EcMasterDemoSyn2067429tAtEmLog_019:40:555
1788739810,0EcMasterDemoSyn1789729tAtEmLog_023:34:115
1554739810,0EcMasterDemoSyn1555729tAtEmLog_020:36:425
43539800,0EcMasterDemoSyn44629tAtEmLog_020:06:185
3178339800,0EcMasterDemoSyn3179329tAtEmLog_021:52:455
1512539790,0EcMasterDemoSyn1513529tAtEmLog_019:30:475
919339780,0EcMasterDemoSyn920329tAtEmLog_020:21:305
919339780,0EcMasterDemoSyn920329tAtEmLog_020:21:295
77239780,0EcMasterDemoSyn78929tAtEmLog_019:05:275
325639780,0EcMasterDemoSyn326629tAtEmLog_020:11:215
2588739780,0EcMasterDemoSyn2589729tAtEmLog_023:39:145
1832239780,0EcMasterDemoSyn1833229tAtEmLog_020:41:465
122439780,0EcMasterDemoSyn123529tAtEmLog_023:44:195
997339770,0EcMasterDemoSyn998329tAtEmLog_023:29:075
410439770,0EcMasterDemoSyn411429tAtEmLog_023:24:015
3174639770,0EcMasterDemoSyn3175629tAtEmLog_022:58:415
2659739770,0EcMasterDemoSyn2660729tAtEmLog_020:56:595
2382039770,0EcMasterDemoSyn2383029tAtEmLog_019:46:005
342639760,0EcMasterDemoSyn343629tAtEmLog_000:35:015
3211339750,0EcMasterDemoSyn3212329tAtEmLog_020:01:125
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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