You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2024-11-22 - 17:13
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Fri Nov 22, 2024 12:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
107139880,0EcMasterDemoSyn108129tAtEmLog_008:48:265
2436039860,0EcMasterDemoSyn2437029tAtEmLog_012:21:235
1958939860,0EcMasterDemoSyn1959929tAtEmLog_012:36:365
625639830,0EcMasterDemoSyn626629tAtEmLog_009:29:005
625639830,0EcMasterDemoSyn626629tAtEmLog_009:29:005
2011839830,0EcMasterDemoSyn2012829tAtEmLog_009:39:085
611039820,0EcMasterDemoSyn612029tAtEmLog_011:35:465
3005939820,0EcMasterDemoSyn3006929tAtEmLog_010:34:555
2948939820,0EcMasterDemoSyn2949929tAtEmLog_007:42:315
2098039820,0EcMasterDemoSyn2099029tAtEmLog_010:50:075
1824039820,0EcMasterDemoSyn1825029tAtEmLog_007:22:145
1647939820,0EcMasterDemoSyn1648929tAtEmLog_008:18:005
1527939820,0EcMasterDemoSyn1528929tAtEmLog_011:40:505
984139810,0EcMasterDemoSyn985129tAtEmLog_007:07:015
814539810,0EcMasterDemoSyn815529tAtEmLog_008:02:485
536739810,0EcMasterDemoSyn537729tAtEmLog_007:57:445
2754039810,0EcMasterDemoSyn2755029tAtEmLog_008:38:175
201739810,0EcMasterDemoSyn202729tAtEmLog_011:15:285
1009339810,0EcMasterDemoSyn1010629tAtEmLog_012:31:325
659739800,0EcMasterDemoSyn660729tAtEmLog_008:58:345
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional