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2025-04-02 - 04:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Wed Apr 02, 2025 00:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
238133911100,1EcMasterDemoSyn23819-21runintdemo5min00:24:535
238133911100,1EcMasterDemoSyn23819-21runintdemo5min00:24:525
6940391270,3EcMasterDemoSyn129899cyclictest23:03:463
21081391090,4EcMasterDemoSyn129599cyclictest20:46:510
9904391030,0EcMasterDemoSyn991029tAtEmLog_021:37:345
1665939920,0EcMasterDemoSyn1666929tAtEmLog_000:19:495
362139910,0EcMasterDemoSyn363129tAtEmLog_019:10:305
916039900,0EcMasterDemoSyn917029tAtEmLog_019:20:405
214239900,0EcMasterDemoSyn215329tAtEmLog_022:38:245
445239880,0EcMasterDemoSyn446429tAtEmLog_022:18:065
445239880,0EcMasterDemoSyn446429tAtEmLog_022:18:065
2408139880,0EcMasterDemoSyn2409129tAtEmLog_022:53:365
1003339880,0EcMasterDemoSyn1004329tAtEmLog_020:26:345
2933839870,0EcMasterDemoSyn2934829tAtEmLog_019:56:085
2082939860,0EcMasterDemoSyn2083929tAtEmLog_023:13:545
2937339850,0EcMasterDemoSyn2938329tAtEmLog_021:02:035
2658139850,0EcMasterDemoSyn2659129tAtEmLog_019:51:055
2383839840,0EcMasterDemoSyn2384829tAtEmLog_020:51:565
1586939840,0EcMasterDemoSyn1587929tAtEmLog_022:48:325
694039830,0EcMasterDemoSyn695029tAtEmLog_023:03:455
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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