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2024-07-16 - 08:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Mon Jul 15, 2024 12:44:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2840339166440,0EcMasterDemoSyn0-21swapper/512:35:395
152623984050,0EcMasterDemoSyn0-21swapper/512:29:075
23353984020,0EcMasterDemoSyn0-21swapper/508:04:305
225913984000,0EcMasterDemoSyn0-21swapper/510:48:355
203373984000,0EcMasterDemoSyn0-21swapper/508:21:565
190093984000,0EcMasterDemoSyn0-21swapper/507:13:395
53603983990,0EcMasterDemoSyn0-21swapper/512:23:405
159323983970,0EcMasterDemoSyn49-21ksoftirqd/508:18:185
287293983960,0EcMasterDemoSyn0-21swapper/507:24:125
199183983950,0EcMasterDemoSyn0-21swapper/509:20:245
299083983930,0EcMasterDemoSyn0-21swapper/512:19:405
148083983920,0EcMasterDemoSyn0-21swapper/507:42:215
69713983910,0EcMasterDemoSyn0-21swapper/508:42:175
69713983910,0EcMasterDemoSyn0-21swapper/508:42:165
307933983910,0EcMasterDemoSyn0-21swapper/508:33:555
34823983900,0EcMasterDemoSyn0-21swapper/511:47:455
19623983890,0EcMasterDemoSyn0-21swapper/508:36:495
260903983880,0EcMasterDemoSyn0-21swapper/511:42:185
8273983870,0EcMasterDemoSyn0-21swapper/510:02:085
88423983860,0EcMasterDemoSyn0-21swapper/511:33:145
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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