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2024-11-23 - 11:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack5slot1.osadl.org (updated Sat Nov 23, 2024 00:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2565398100,1EcMasterDemoSyn2574-21runintdemo5min19:22:136
18749392010,0EcMasterDemoSyn0-21swapper/622:04:286
3218239910,0EcMasterDemoSyn3219229tAtEmLog_019:17:095
2789939880,0EcMasterDemoSyn2790929tAtEmLog_020:07:515
820339870,0EcMasterDemoSyn821329tAtEmLog_023:20:315
1995139870,0EcMasterDemoSyn1996229tAtEmLog_023:50:575
3075239850,0EcMasterDemoSyn3076229tAtEmLog_000:21:225
1207339850,0EcMasterDemoSyn1208329tAtEmLog_020:38:165
1874939840,0EcMasterDemoSyn1875929tAtEmLog_022:04:285
2797139830,0EcMasterDemoSyn2798129tAtEmLog_023:56:025
1095639830,0EcMasterDemoSyn1096629tAtEmLog_021:18:515
298739820,0EcMasterDemoSyn299729tAtEmLog_021:13:465
2650739820,0EcMasterDemoSyn2651729tAtEmLog_022:29:505
1841839820,0EcMasterDemoSyn1843029tAtEmLog_000:11:155
1407539820,0EcMasterDemoSyn1408529tAtEmLog_019:42:305
971939810,0EcMasterDemoSyn972929tAtEmLog_023:00:145
2596239810,0EcMasterDemoSyn2597229tAtEmLog_021:03:385
2042539810,0EcMasterDemoSyn2043529tAtEmLog_020:53:295
2873039790,0EcMasterDemoSyn2874029tAtEmLog_021:08:425
269539790,0EcMasterDemoSyn270729tAtEmLog_021:34:035
1959439790,0EcMasterDemoSyn1960429tAtEmLog_019:52:385
1681839790,0EcMasterDemoSyn1682829tAtEmLog_023:05:195
3065739780,0EcMasterDemoSyn3066729tAtEmLog_020:12:565
2559539780,0EcMasterDemoSyn2560529tAtEmLog_022:50:075
1077539780,0EcMasterDemoSyn1078529tAtEmLog_021:59:245
379639770,0EcMasterDemoSyn380629tAtEmLog_020:23:045
33839770,0EcMasterDemoSyn34829tAtEmLog_023:15:275
2513139770,0EcMasterDemoSyn2514129tAtEmLog_020:02:475
243439770,0EcMasterDemoSyn244429tAtEmLog_022:34:535
1907239770,0EcMasterDemoSyn1908229tAtEmLog_021:23:545
1395339760,0EcMasterDemoSyn1396329tAtEmLog_023:25:375
1225939760,0EcMasterDemoSyn1226929tAtEmLog_000:31:315
1225939760,0EcMasterDemoSyn1226929tAtEmLog_000:31:305
256539750,0EcMasterDemoSyn257529tAtEmLog_019:22:145
1033839750,0EcMasterDemoSyn1034829tAtEmLog_022:19:415
291612720,0sleep70-21swapper/720:10:147
178602660,0sleep10-21swapper/121:22:491
25842620,2sleep763-21ksoftirqd/721:54:117
245312590,0sleep00-21swapper/022:07:350
251962580,1sleep50-21swapper/521:27:175
41042550,1sleep549-21ksoftirqd/500:01:375
2661999509,29cyclictest421-21systemd-journal20:58:341
2661299391,27cyclictest5328-21ps19:27:170
26619993811,16cyclictest421-21systemd-journal20:28:071
2661299368,16cyclictest27710-21runintdemo5min23:25:360
2661999350,24cyclictest421-21systemd-journal20:17:591
2661299358,16cyclictest421-21systemd-journal21:34:040
2661999336,16cyclictest421-21systemd-journal22:09:331
26619993310,16cyclictest0-21swapper/120:23:041
26619993310,15cyclictest0-21swapper/123:40:491
2661999329,16cyclictest0-21swapper/122:19:421
2661999325,16cyclictest18755-21ps22:04:291
2661299329,19cyclictest421-21systemd-journal22:34:520
2661299329,16cyclictest0-21swapper/019:47:340
2661299325,16cyclictest421-21systemd-journal21:23:530
2661299318,15cyclictest0-21swapper/020:12:560
2661999303,16cyclictest421-21systemd-journal20:48:241
26619993010,15cyclictest0-21swapper/120:33:111
2661299308,15cyclictest0-21swapper/020:02:470
2661299303,16cyclictest0-21swapper/019:52:370
2661299302,16cyclictest421-21systemd-journal21:28:570
2661299292,16cyclictest0-21swapper/021:59:240
2661299281,16cyclictest2759-21ps21:54:210
2661299281,16cyclictest0-21swapper/021:44:100
18442280,0sleep60-21swapper/622:55:136
2661999274,16cyclictest0-21swapper/121:13:471
2661299273,16cyclictest0-21swapper/019:32:200
26636992622,4cyclictest240-21printk00:16:194
26628992625,1cyclictest240-21printk23:00:153
26623992623,2cyclictest240-21printk20:38:172
2661299260,15cyclictest0-21swapper/022:19:400
26636992524,1cyclictest240-21printk23:56:024
26636992524,1cyclictest240-21printk00:36:354
26628992524,1cyclictest240-21printk22:55:103
26628992524,1cyclictest240-21printk22:50:063
26628992524,1cyclictest240-21printk21:23:553
26623992523,2cyclictest240-21printk19:52:382
2661999253,15cyclictest0-21swapper/121:18:491
26612992524,1cyclictest240-21printk23:45:530
2661299252,16cyclictest0-21swapper/022:29:500
2661299252,16cyclictest0-21swapper/019:17:090
2661299251,16cyclictest0-21swapper/020:07:500
26628992423,1cyclictest240-21printk22:14:373
26628992423,1cyclictest240-21printk21:49:153
26628992423,1cyclictest240-21printk21:03:373
26623992423,1cyclictest240-21printk20:07:522
2661999244,11cyclictest0-21swapper/119:55:091
2661299244,12cyclictest0-21swapper/022:45:120
2661299243,13cyclictest0-21swapper/023:20:010
2661299240,16cyclictest0-21swapper/021:49:150
26628992322,1cyclictest240-21printk23:05:193
26623992322,1cyclictest240-21printk00:26:262
26623992321,1cyclictest240-21printk19:57:432
2661999234,12cyclictest0-21swapper/123:45:091
2661999234,11cyclictest0-21swapper/121:35:091
2661299234,12cyclictest0-21swapper/000:30:100
2661299234,12cyclictest0-21swapper/000:30:100
2661299234,11cyclictest0-21swapper/023:55:130
2661299234,11cyclictest0-21swapper/021:10:120
2661299234,11cyclictest0-21swapper/000:20:110
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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