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2024-11-22 - 10:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack5slot1.osadl.org (updated Fri Nov 22, 2024 00:44:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2410721000,0sleep00-21swapper/020:20:190
2132939860,0EcMasterDemoSyn2133929tAtEmLog_022:34:565
1935539860,0EcMasterDemoSyn1936529tAtEmLog_000:26:285
1246539850,0EcMasterDemoSyn1247529tAtEmLog_000:21:255
2227739840,0EcMasterDemoSyn2228729tAtEmLog_022:14:395
720539830,0EcMasterDemoSyn721529tAtEmLog_023:30:435
634639830,0EcMasterDemoSyn635629tAtEmLog_022:04:315
1447639830,0EcMasterDemoSyn1448629tAtEmLog_021:49:175
927439820,0EcMasterDemoSyn928429tAtEmLog_023:56:035
912839820,0EcMasterDemoSyn913829tAtEmLog_020:53:315
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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