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2025-04-02 - 04:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot0.osadl.org (updated Wed Apr 02, 2025 00:44:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2122321280,2sleep0728299cyclictest21:12:330
74021250,0sleep0732-21cp23:44:070
2674021190,1sleep3729999cyclictest22:10:593
6822210533,44sleep30-21swapper/319:06:563
1864021000,3sleep325-21rcuop/119:35:123
309332970,2sleep30-21swapper/322:05:183
212172960,6sleep20-21swapper/222:13:342
696829535,56sleep10-21swapper/119:08:461
36452950,2sleep20-21swapper/221:47:292
194862940,0sleep019488-21pmu-power21:15:210
71372920,1sleep30-21swapper/323:10:463
273132890,2sleep027293-21sshd21:58:500
96152880,1sleep20-21swapper/223:57:222
286822860,2sleep30-21swapper/322:51:033
146052860,0sleep00-21swapper/000:20:370
43332850,2sleep14329-21bash00:13:091
176712850,1sleep117669-21bash00:04:351
155832840,1sleep20-21swapper/222:00:402
53112820,4sleep3729999cyclictest22:21:093
308402820,2sleep00-21swapper/023:31:350
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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