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2024-11-22 - 16:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot0.osadl.org (updated Fri Nov 22, 2024 12:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
983121520,3sleep01584199cyclictest12:09:570
1267021430,1sleep012667-21sshd12:27:010
3142121350,4sleep21584399cyclictest12:20:132
1226921180,3sleep10-21swapper/109:17:091
15475210332,44sleep30-21swapper/307:08:433
1533429733,43sleep10-21swapper/107:07:011
140822890,1sleep00-21swapper/011:33:500
220022880,1sleep10-21swapper/110:58:121
189192880,2sleep318912-21bash12:33:133
297792860,1sleep10-21swapper/112:03:131
297792860,1sleep10-21swapper/112:03:131
80652850,1sleep30-21swapper/311:55:383
252862850,5sleep31584499cyclictest09:54:263
235442850,4sleep21584399cyclictest09:31:202
176992850,0sleep00-21swapper/010:39:320
160292850,1sleep216031-21sshd10:26:152
88992840,2sleep10-21swapper/109:20:091
29512840,2sleep12949-21sshd11:52:271
233282840,2sleep31847-21nfsd10:46:043
22822820,2sleep31848-21nfsd11:15:583
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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