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2024-07-16 - 08:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot0.osadl.org (updated Mon Jul 15, 2024 12:44:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1701821440,0sleep117019-21sshd10:22:251
2852821340,0sleep228527-21sshd11:13:202
1786021280,1sleep01848-21nfsd09:46:010
59521250,0sleep1596-21sshd12:09:571
299421240,3sleep00-21swapper/011:00:470
1527221230,4sleep13233999cyclictest12:18:001
2025921210,3sleep20-21swapper/211:35:282
31940210233,56sleep30-21swapper/307:08:103
51752940,1sleep11847-21nfsd09:31:231
311512940,2sleep131145-21ls10:30:311
87772920,3sleep18767-21sshd10:51:301
87772920,3sleep18767-21sshd10:51:301
3197829232,48sleep10-21swapper/107:08:411
287072920,2sleep30-21swapper/309:43:553
201242880,3sleep30-21swapper/310:52:413
201242880,3sleep30-21swapper/310:52:413
144562880,3sleep03233399cyclictest10:02:240
4112850,2sleep30-21swapper/310:17:223
187232850,1sleep018720-21sshd12:28:120
165312840,1sleep116530-21sshd09:12:401
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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