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2024-07-27 - 14:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Sat Jul 27, 2024 12:49:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
242162720chrt46050irq/122-QMan09:24:360
242162720chrt46050irq/122-QMan09:24:360
46050490irq/122-QManpo29357-2109:24:360
46050490irq/122-QManpo29357-2109:24:360
46650480irq/116-QManpo29883-2109:24:363
71460rcu_preempt26959-21runrttasks11:03:490
71460rcu_preempt26959-21runrttasks11:03:490
71450rcu_preempt0-21swapper/310:59:043
71450rcu_preempt0-21swapper/310:59:043
71450rcu_preempt0-21swapper/213:03:142
71450rcu_preempt0-21swapper/213:03:142
71450rcu_preempt0-21swapper/010:50:590
71450rcu_preempt0-21swapper/010:50:590
71450rcu_preempt0-21swapper/010:50:590
71450rcu_preempt0-21swapper/010:46:560
71450rcu_preempt0-21swapper/010:46:560
71450rcu_preempt0-21swapper/010:29:270
71450rcu_preempt0-21swapper/010:29:270
71450rcu_preempt0-21swapper/010:29:270
71450rcu_preempt0-21swapper/010:29:270
71440rcu_preempt0-21swapper/010:24:180
71440rcu_preempt0-21swapper/010:24:180
71440rcu_preempt0-21swapper/010:24:180
71440rcu_preempt0-21swapper/010:14:260
71440rcu_preempt0-21swapper/010:14:260
8742994315cyclictest0-21swapper/111:03:241
8742994315cyclictest0-21swapper/111:03:241
71430rcu_preempt29062-21sh12:05:080
71430rcu_preempt29062-21sh12:05:080
71430rcu_preempt29062-21sh12:05:080
71430rcu_preempt0-21swapper/211:54:372
71430rcu_preempt0-21swapper/211:54:372
71430rcu_preempt0-21swapper/211:54:372
71430rcu_preempt0-21swapper/210:58:482
71430rcu_preempt0-21swapper/210:58:482
71430rcu_preempt0-21swapper/210:23:402
71430rcu_preempt0-21swapper/210:23:402
71430rcu_preempt0-21swapper/010:08:410
71430rcu_preempt0-21swapper/010:08:410
71430rcu_preempt0-21swapper/009:47:250
71430rcu_preempt0-21swapper/009:47:250
46250430irq/120-QManpo29890-2109:24:361
8742994222cyclictest14359-21diskstats09:38:541
8742994222cyclictest14359-21diskstats09:38:541
8742994221cyclictest11414-21/usr/sbin/munin09:34:011
8742994221cyclictest11414-21/usr/sbin/munin09:34:011
8742994217cyclictest8626-21runrttasks12:03:281
8742994217cyclictest8626-21runrttasks12:03:281
71420rcu_preempt7534-21ssh12:24:080
71420rcu_preempt7534-21ssh12:24:080
71420rcu_preempt14332-21ssh11:39:090
71420rcu_preempt14332-21ssh11:39:090
71420rcu_preempt14332-21ssh11:39:090
71420rcu_preempt14329-21kworker/u8:211:56:270
71420rcu_preempt14329-21kworker/u8:211:56:270
71420rcu_preempt14329-21kworker/u8:211:56:270
71420rcu_preempt0-21swapper/312:08:203
71420rcu_preempt0-21swapper/312:08:203
71420rcu_preempt0-21swapper/312:08:203
71420rcu_preempt0-21swapper/311:39:253
71420rcu_preempt0-21swapper/311:39:253
71420rcu_preempt0-21swapper/311:39:253
71420rcu_preempt0-21swapper/110:29:181
71420rcu_preempt0-21swapper/110:29:181
71420rcu_preempt0-21swapper/110:29:181
71420rcu_preempt0-21swapper/110:29:181
71420rcu_preempt0-21swapper/011:14:440
71420rcu_preempt0-21swapper/011:14:440
71420rcu_preempt0-21swapper/011:14:440
46650420irq/116-QManpo29029-2109:24:363
8742994121cyclictest5637-21meminfo11:24:011
8742994121cyclictest5637-21meminfo11:24:011
8742994121cyclictest4321-21memory12:19:031
8742994121cyclictest4321-21memory12:19:031
8742994120cyclictest905-21ntp_states08:59:071
8742994120cyclictest905-21ntp_states08:59:071
8742994120cyclictest32739-21memory11:14:041
8742994120cyclictest32739-21memory11:14:041
8742994120cyclictest32739-21memory11:14:041
8742994119cyclictest16193-21munin-run11:43:381
8742994119cyclictest16193-21munin-run11:43:381
8742994119cyclictest16193-21munin-run11:43:381
71410rcu_preempt20664-21seq12:48:321
71410rcu_preempt20664-21seq12:48:321
71410rcu_preempt0-21swapper/312:23:323
71410rcu_preempt0-21swapper/312:23:323
71410rcu_preempt0-21swapper/012:36:410
71410rcu_preempt0-21swapper/012:36:410
71410rcu_preempt0-21swapper/009:40:460
71410rcu_preempt0-21swapper/009:40:460
8742994020cyclictest27969-21ntp_states10:04:051
8742994020cyclictest27969-21ntp_states10:04:051
8742994020cyclictest24706-21munin-run11:58:381
8742994020cyclictest24706-21munin-run11:58:381
8742994020cyclictest24706-21munin-run11:58:381
8742994020cyclictest16977-21/usr/sbin/munin09:43:531
8742994020cyclictest16977-21/usr/sbin/munin09:43:531
71400rcu_preempt0-21swapper/308:08:403
71400rcu_preempt0-21swapper/308:08:403
71400rcu_preempt0-21swapper/308:08:403
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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