You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2024-11-22 - 09:15
OSADL QA Farm

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Default latency plot of system in rack #3, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
Special  All - All RT - Optimization - Ethernet - Thumbnails - Next 		  
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack3slot4.osadl.org (updated Fri Nov 22, 2024 00:46:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)		T*(,W**)
latency
(µs)		CmdPIDPrioCmd
3824987233493321,9sleep13820549-21kworker/1:4+events@
dbs_work_handler		19:05:191
382646799162124,31cyclictest3948040-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork		22:23:130
382648099137123,7cyclictest3905726-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork		21:43:073
382646799135101,26cyclictest3852103-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork		20:17:490
382646799135101,26cyclictest3852103-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork		20:17:490
3826467991331,115cyclictest3937626-21ssh22:05:230
3826467991331,115cyclictest3937626-21ssh22:05:220
38264679912995,26cyclictest3898489-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork		21:48:070
38264679912591,26cyclictest3991742-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork		23:03:210
38264679912488,27cyclictest4074945-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork		00:06:560
38264679912463,49cyclictest64350irq/528-eth0-Tx00:15:350
3826467991181,107cyclictest0-21swapper/021:10:330
38264679911480,27cyclictest3921863-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork		21:58:100
38264679911420,39cyclictest15-21rcuc/022:25:330
3826467991132,88cyclictest3858654-21acpi20:30:110
3826467991132,88cyclictest3858654-21acpi20:30:110
3826467991121,63cyclictest0-21swapper/023:41:510
3826467991121,63cyclictest0-21swapper/023:41:500
3826467991112,98cyclictest0-21swapper/023:35:180
3826467991111,91cyclictest3826907-21cpu19:10:190
38264769911096,7cyclictest3948040-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork		22:18:122
38264769911096,7cyclictest3948040-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork		22:18:112
38264679911058,26cyclictest3868358-21wc20:55:010
38264679911035,37cyclictest4074945-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork		00:11:140
38264679910936,50cyclictest3832233-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork		19:52:500
38264679910929,55cyclictest4068196-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork		00:02:420
3826467991081,96cyclictest15-21rcuc/022:15:010
3826467991081,96cyclictest15-21rcuc/022:15:000
3826467991081,88cyclictest0-21swapper/021:05:190
3826467991081,66cyclictest3995040-21ssh22:54:570
3826467991081,66cyclictest3995040-21ssh22:54:560
3826467991061,88cyclictest0-21swapper/021:32:440
38264769910592,6cyclictest3979007-21kworker/u12:4+events_unbound@
flush_memcg_stats_dwork		22:43:182
38264769910592,6cyclictest3979007-21kworker/u12:4+events_unbound@
flush_memcg_stats_dwork		22:43:172
38264679910564,31cyclictest64250irq/527-eth0-Tx23:50:260
38264679910564,31cyclictest64250irq/527-eth0-Tx23:50:260
38264679910550,37cyclictest0-21swapper/020:20:400
38264679910472,22cyclictest64450irq/529-eth0-Tx21:25:040
38264679910354,32cyclictest0-21swapper/019:15:410
38264679910354,32cyclictest0-21swapper/019:15:400
3826467991032,59cyclictest64250irq/527-eth0-Tx21:40:130
3826467991031,58cyclictest0-21swapper/021:23:020
38264899910296,3cyclictest0-21swapper/522:23:135
38264809910288,7cyclictest3921863-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork		21:53:083
3826467991026,51cyclictest13-21ksoftirqd/022:57:330
38264679910248,40cyclictest0-21swapper/023:07:460
38264679910239,26cyclictest3874185-21diskmemload23:25:200
3826467991021,71cyclictest4013296-21awk23:10:340
38264679910152,34cyclictest0-21swapper/022:40:110
38264679910152,34cyclictest0-21swapper/022:40:100
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional