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2024-11-22 - 17:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot4.osadl.org (updated Fri Nov 22, 2024 12:46:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7722369912192,21cyclictest779959-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
07:29:350
77224199120106,7cyclictest828513-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
09:24:491
77225199118105,6cyclictest898943-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
11:04:573
77226099114108,3cyclictest0-21swapper/510:24:545
77226099113108,2cyclictest0-21swapper/510:49:555
7722519911197,7cyclictest1015973-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
12:25:073
7722519911197,7cyclictest1015973-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
12:25:063
7722369911183,20cyclictest921670-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
10:49:550
7722369911083,19cyclictest885525-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
10:24:530
7722369910950,47cyclictest13-21ksoftirqd/010:01:200
7722369910663,36cyclictest842347-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
09:49:500
772236991054,96cyclictest0-21swapper/011:14:080
772236991054,96cyclictest0-21swapper/011:14:080
772236991051,86cyclictest0-21swapper/007:30:390
7722369910354,42cyclictest764031-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
07:20:280
772236991031,88cyclictest0-21swapper/008:30:370
772236991031,88cyclictest0-21swapper/008:30:370
7722369910258,27cyclictest0-21swapper/011:30:340
7722369910015,72cyclictest64450irq/529-eth0-Tx11:35:070
7722369910015,72cyclictest64450irq/529-eth0-Tx11:35:060
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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