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2024-11-25 - 16:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack3slot3.osadl.org (updated Mon Nov 25, 2024 12:46:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120501120irq/42-ahci0-21swapper/807:08:2510
5741210991sleep00-21swapper/007:06:120
5851210794sleep20-21swapper/207:07:374
120501070irq/42-ahci0-21swapper/707:08:549
14850990irq/18-uhci_hcd0-21swapper/407:05:096
118450960irq/18-i801_smb0-21swapper/1107:05:083
12050940irq/42-ahci0-21swapper/107:09:191
2013050920irq/52-eth0-rx-0-21swapper/507:07:277
2013050920irq/52-eth0-rx-0-21swapper/307:06:305
128050910irq/18-parport00-21swapper/907:05:1711
128050790irq/18-parport00-21swapper/1007:07:232
288826454sleep60-21swapper/607:05:048
618499320cyclictest0-21swapper/008:28:420
6184993114cyclictest0-21swapper/007:24:500
6184993114cyclictest0-21swapper/007:24:490
618499310cyclictest0-21swapper/009:14:340
6184992521cyclictest0-21swapper/009:28:580
6184992423cyclictest0-21swapper/009:16:360
618499240cyclictest0-21swapper/009:21:560
6231992019cyclictest0-21swapper/1109:26:453
6231992019cyclictest0-21swapper/1109:21:523
118450200irq/18-i801_smb0-21swapper/010:27:200
6184991917cyclictest0-21swapper/009:30:180
618499190cyclictest0-21swapper/009:08:370
622599181cyclictest13250irq/18-ehci_hcd11:52:002
622599181cyclictest13250irq/18-ehci_hcd10:11:582
622599181cyclictest128050irq/18-parport008:21:442
622599181cyclictest118450irq/18-i801_smb10:05:252
622499181cyclictest761ksoftirqd/912:30:1411
622499181cyclictest761ksoftirqd/912:00:2311
622499181cyclictest761ksoftirqd/911:30:0211
622499181cyclictest761ksoftirqd/907:55:2311
622499181cyclictest0-21swapper/912:25:1811
622499181cyclictest0-21swapper/912:20:0011
622499181cyclictest0-21swapper/911:57:0111
622499181cyclictest0-21swapper/911:48:5011
622499181cyclictest0-21swapper/911:34:0611
622499181cyclictest0-21swapper/911:20:1111
622499181cyclictest0-21swapper/911:15:2411
622499181cyclictest0-21swapper/911:07:0911
622499181cyclictest0-21swapper/910:41:0611
622499181cyclictest0-21swapper/910:35:0711
622499181cyclictest0-21swapper/910:20:2211
622499181cyclictest0-21swapper/910:05:2811
622499181cyclictest0-21swapper/910:00:5111
622499181cyclictest0-21swapper/909:58:1411
622499181cyclictest0-21swapper/909:40:5111
622499181cyclictest0-21swapper/909:35:2811
622499181cyclictest0-21swapper/909:25:3511
622499181cyclictest0-21swapper/909:10:2611
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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