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2024-07-16 - 08:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot3.osadl.org (updated Tue Jul 16, 2024 00:46:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
8752210297sleep70-21swapper/719:09:039
122501010irq/42-ahci0-21swapper/319:08:585
12250990irq/42-ahci0-21swapper/119:09:591
1105350960irq/53-eth0-tx-0-21swapper/219:05:254
1105250960irq/52-eth0-rx-0-21swapper/419:05:446
1105250910irq/52-eth0-rx-0-21swapper/519:06:117
12250900irq/42-ahci0-21swapper/819:08:3710
847726955sleep00-21swapper/019:06:080
12250690irq/42-ahci0-21swapper/1019:06:072
858826555sleep60-21swapper/619:07:388
860726354sleep90-21swapper/919:07:5311
845926254sleep110-21swapper/1119:05:553
897899330cyclictest0-21swapper/1120:16:353
8943992928cyclictest0-21swapper/020:19:310
8943992719cyclictest0-21swapper/022:35:360
897699205cyclictest0-21swapper/922:47:5011
897699181cyclictest29669-1kworker/9:1H22:02:3111
897699181cyclictest0-21swapper/922:41:4911
897699181cyclictest0-21swapper/921:53:5211
897699181cyclictest0-21swapper/920:30:2811
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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