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2024-11-26 - 00:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot3.osadl.org (updated Mon Nov 25, 2024 12:46:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120501120irq/42-ahci0-21swapper/807:08:2510
5741210991sleep00-21swapper/007:06:120
5851210794sleep20-21swapper/207:07:374
120501070irq/42-ahci0-21swapper/707:08:549
14850990irq/18-uhci_hcd0-21swapper/407:05:096
118450960irq/18-i801_smb0-21swapper/1107:05:083
12050940irq/42-ahci0-21swapper/107:09:191
2013050920irq/52-eth0-rx-0-21swapper/507:07:277
2013050920irq/52-eth0-rx-0-21swapper/307:06:305
128050910irq/18-parport00-21swapper/907:05:1711
128050790irq/18-parport00-21swapper/1007:07:232
288826454sleep60-21swapper/607:05:048
618499320cyclictest0-21swapper/008:28:420
6184993114cyclictest0-21swapper/007:24:500
6184993114cyclictest0-21swapper/007:24:490
618499310cyclictest0-21swapper/009:14:340
6184992521cyclictest0-21swapper/009:28:580
6184992423cyclictest0-21swapper/009:16:360
618499240cyclictest0-21swapper/009:21:560
6231992019cyclictest0-21swapper/1109:26:453
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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