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2024-11-21 - 16:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Thu Nov 21, 2024 12:46:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
25619210894sleep50-21swapper/507:07:457
25465210894sleep20-21swapper/207:05:414
25577210592sleep70-21swapper/707:07:109
1280501020irq/18-parport00-21swapper/807:07:2510
1184501020irq/18-i801_smb0-21swapper/107:07:251
128050990irq/18-parport00-21swapper/407:07:556
118450980irq/18-i801_smb0-21swapper/307:07:585
12050900irq/42-ahci0-21swapper/907:07:1411
128050840irq/18-parport00-21swapper/1007:09:392
128050790irq/18-parport00-21swapper/1107:05:023
2553325853sleep60-21swapper/607:06:338
2266225753sleep00-21swapper/007:05:030
2594399500cyclictest0-21swapper/009:28:050
25993992914cyclictest0-21swapper/1110:17:513
2599299259cyclictest831ksoftirqd/1010:15:222
2599299258cyclictest831ksoftirqd/1008:44:242
2599299258cyclictest831ksoftirqd/1008:34:172
2599299258cyclictest831ksoftirqd/1008:23:222
2599299258cyclictest831ksoftirqd/1008:05:182
25963992524cyclictest13250irq/18-ehci_hcd09:28:135
25956992524cyclictest13250irq/18-ehci_hcd09:28:014
2599299247cyclictest831ksoftirqd/1008:53:542
2594399240cyclictest0-21swapper/008:09:500
25947992221cyclictest13250irq/18-ehci_hcd09:28:131
25991992019cyclictest13250irq/18-ehci_hcd09:28:1011
2599299192cyclictest831ksoftirqd/1008:45:192
2599299192cyclictest12050irq/42-ahci10:25:422
2599299192cyclictest12050irq/42-ahci10:25:422
128050190irq/18-parport00-21swapper/407:39:486
25992991817cyclictest8627-21missed_timers08:10:222
25992991817cyclictest831ksoftirqd/1011:40:112
2599299181cyclictest831ksoftirqd/1012:35:162
2599299181cyclictest831ksoftirqd/1011:50:172
2599299181cyclictest831ksoftirqd/1011:20:262
2599299181cyclictest831ksoftirqd/1010:40:292
2599299181cyclictest831ksoftirqd/1010:40:292
2599299181cyclictest831ksoftirqd/1010:05:012
2599299181cyclictest831ksoftirqd/1009:00:102
2599299181cyclictest831ksoftirqd/1007:50:112
2599299181cyclictest128050irq/18-parport011:28:402
2599299181cyclictest12050irq/42-ahci11:10:022
2599299181cyclictest118450irq/18-i801_smb10:38:372
2599199181cyclictest24361-1kworker/9:2H10:56:1611
2599199181cyclictest24361-1kworker/9:2H07:41:3611
2599199181cyclictest0-21swapper/911:55:1811
2599199181cyclictest0-21swapper/911:54:3811
2599199181cyclictest0-21swapper/908:31:0211
25987991816cyclictest12205-21switchtime12:00:2910
25979991816cyclictest26679-21sensors12:20:288
25977991817cyclictest0-21swapper/511:20:347
25977991816cyclictest6131-21qemu-kvm08:12:027
25977991816cyclictest25701-21qemu-kvm07:35:347
25977991816cyclictest17549-21qemu-kvm09:45:147
25947991816cyclictest27215-21snmp_rack3slot907:10:111
25947991816cyclictest2216-21snmp_rack3slot912:32:061
25992991716cyclictest831ksoftirqd/1012:30:372
25992991716cyclictest831ksoftirqd/1011:55:002
25992991716cyclictest831ksoftirqd/1011:00:162
25992991716cyclictest831ksoftirqd/1010:20:302
25992991716cyclictest831ksoftirqd/1010:05:022
25992991716cyclictest831ksoftirqd/1010:05:012
25992991716cyclictest28373-21snmp_rack3slot907:55:102
25992991716cyclictest207501cat07:45:012
25992991716cyclictest207501cat07:45:002
25992991716cyclictest19409-21kworker/10:012:20:252
25992991716cyclictest18652-21cpuspeed_turbos09:10:102
25992991716cyclictest12682-21snmp_rack3slot912:00:372
25992991716cyclictest1218-21snmp_easybox.os09:35:112
25992991716cyclictest0-21swapper/1012:25:252
25992991716cyclictest0-21swapper/1009:40:022
25992991716cyclictest0-21swapper/1008:17:322
2599299170cyclictest95582sleep1010:30:112
2599299170cyclictest95582sleep1010:30:102
2599299170cyclictest89752chrt11:14:272
2599299170cyclictest831ksoftirqd/1012:10:252
2599299170cyclictest831ksoftirqd/1011:35:272
2599299170cyclictest831ksoftirqd/1011:15:132
2599299170cyclictest831ksoftirqd/1010:50:012
2599299170cyclictest831ksoftirqd/1010:10:302
2599299170cyclictest831ksoftirqd/1009:50:142
2599299170cyclictest831ksoftirqd/1009:30:142
2599299170cyclictest831ksoftirqd/1009:15:152
2599299170cyclictest831ksoftirqd/1008:25:132
2599299170cyclictest831ksoftirqd/1008:00:282
2599299170cyclictest831ksoftirqd/1008:00:272
2599299170cyclictest831ksoftirqd/1007:40:122
2599299170cyclictest831ksoftirqd/1007:30:282
2599299170cyclictest831ksoftirqd/1007:25:142
2599299170cyclictest831ksoftirqd/1007:15:132
2599299170cyclictest273112sleep1010:55:022
2599299170cyclictest264782sleep1010:50:382
2599299170cyclictest232632sleep1011:31:072
2599299170cyclictest208292sleep1012:15:122
2599299170cyclictest2013050irq/52-eth0-rx-09:21:402
2599299170cyclictest2013050irq/52-eth0-rx-07:20:172
2599299170cyclictest188222sleep1009:57:442
2599299170cyclictest167272sleep1009:05:272
2599299170cyclictest165412chrt07:38:042
2599299170cyclictest165382sleep1012:08:102
2599299170cyclictest12050irq/42-ahci08:37:082
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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