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2025-03-31 - 20:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot3.osadl.org (updated Mon Mar 31, 2025 12:46:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
122501140irq/42-ahci0-21swapper/207:09:104
13575210893sleep80-21swapper/807:07:3710
29634501060irq/53-eth0-rx-0-21swapper/307:08:295
122501000irq/42-ahci0-21swapper/107:09:091
2963450880irq/53-eth0-rx-0-21swapper/1107:05:033
2963550870irq/54-eth0-tx-0-21swapper/707:05:259
2963450810irq/53-eth0-rx-0-21swapper/407:05:276
12250760irq/42-ahci0-21swapper/507:05:017
1280027163sleep100-21swapper/1007:05:262
1367126459sleep90-21swapper/907:08:1311
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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