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2024-11-22 - 10:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot3.osadl.org (updated Fri Nov 22, 2024 00:46:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1280501000irq/18-parport00-21swapper/419:06:576
120501000irq/42-ahci0-21swapper/119:08:241
2013050970irq/52-eth0-rx-0-21swapper/719:08:259
118450950irq/18-i801_smb0-21swapper/319:06:545
14850940irq/18-uhci_hcd0-21swapper/219:06:544
2013050920irq/52-eth0-rx-0-21swapper/519:08:087
2013050890irq/52-eth0-rx-0-21swapper/819:05:1710
128050860irq/18-parport00-21swapper/919:10:0111
118450850irq/18-i801_smb0-21swapper/1119:08:143
128050790irq/18-parport00-21swapper/1019:05:252
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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