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2024-07-16 - 08:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot0.osadl.org (updated Tue Jul 16, 2024 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4196991034,58cyclictest698-21dbus-daemon21:33:410
75472950,0sleep10-21swapper/100:06:191
38892810,2sleep6423899cyclictest23:59:206
93042780,0sleep00-21swapper/021:10:230
177872680,0sleep60-21swapper/623:44:226
4231996326,19cyclictest15059-21sshd21:33:405
392626048,9sleep70-21swapper/719:04:037
231562540,0sleep70-21swapper/723:48:077
101062540,0sleep5488-21systemd-journal21:10:285
401625241,8sleep30-21swapper/319:05:193
373225228,8sleep10-21swapper/119:01:331
401825127,8sleep50-21swapper/519:05:215
232672510,1sleep0698-21dbus-daemon00:31:410
200632510,0sleep00-21swapper/023:51:050
80582490,0sleep00-21swapper/021:20:000
62112490,0sleep40-21swapper/421:39:184
393424826,8sleep60-21swapper/619:04:106
150102480,0sleep30-21swapper/323:37:303
48132470,0sleep60-21swapper/622:51:046
149652470,0sleep20-21swapper/223:47:142
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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