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2024-07-16 - 08:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack2slot0.osadl.org (updated Tue Jul 16, 2024 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20062900,0sleep20-21swapper/221:23:272
29302730,0sleep00-21swapper/023:27:100
177362580,0sleep30-21swapper/300:14:593
38572560,0sleep20-21swapper/222:26:152
264412550,1sleep126440-21bash23:26:191
21422550,1sleep32145-21bash21:23:283
9502530,0sleep10-21swapper/100:06:491
145392530,1sleep00-21swapper/019:30:180
314162520,0sleep00-21swapper/023:08:440
295092520,1sleep2311rcuc/222:10:012
26122520,0sleep20-21swapper/200:32:492
251792520,0sleep30-21swapper/321:35:073
213782520,0sleep00-21swapper/023:44:050
152472520,1sleep115243-21lspci23:52:351
65952510,1sleep0101ktimersoftd/023:00:190
65952510,1sleep0101ktimersoftd/023:00:190
15112510,0sleep00-21swapper/023:20:580
91792500,0sleep20-21swapper/223:52:002
207292500,0sleep20-21swapper/223:28:532
13082490,0sleep30-21swapper/322:35:183
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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