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2025-04-02 - 04:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack2slot0.osadl.org (updated Wed Apr 02, 2025 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2353021080,0sleep223495-21sshd00:27:122
204872990,0sleep220486-21id00:20:192
274772950,1sleep227468-21sshd21:30:522
46392900,1sleep3646-21dbus-daemon00:25:163
29672700,0sleep3391rcuc/322:26:493
227482670,0sleep00-21swapper/000:30:180
45482560,0sleep30-21swapper/300:31:413
293102540,1sleep3391rcuc/321:34:103
167342540,1sleep216686-21sshd22:09:452
222692530,0sleep00-21swapper/021:12:040
126862530,0sleep30-21swapper/322:49:203
296562520,0sleep00-21swapper/021:18:530
262032520,0sleep20-21swapper/223:33:492
210782520,1sleep1646-21dbus-daemon22:47:011
201192520,0sleep30-21swapper/300:37:103
304592510,1sleep10-21swapper/100:14:531
253572510,0sleep20-21swapper/200:14:222
10352510,1sleep11013-21sshd21:46:451
163212500,0sleep31-21systemd00:20:003
281702490,0sleep10-21swapper/122:13:531
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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