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2024-11-22 - 16:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack2slot0.osadl.org (updated Fri Nov 22, 2024 12:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1603421010,0sleep015947-21sshd12:11:120
198472620,0sleep10-21swapper/112:00:161
219342560,0sleep20-21swapper/211:29:372
8572540,1sleep1646-21dbus-daemon10:05:331
138872520,1sleep213882-21lspci12:16:392
7762500,0sleep00-21swapper/010:47:370
147062500,1sleep114704-21sshd11:48:381
3452490,0sleep00-21swapper/012:21:060
291212490,0sleep30-21swapper/310:34:543
278522490,0sleep30-21swapper/311:38:303
256572490,1sleep025652-21bash12:34:350
149402490,0sleep00-21swapper/009:50:300
41242480,0sleep00-21swapper/010:35:310
40362480,0sleep00-21swapper/010:22:170
28692480,0sleep00-21swapper/009:00:120
213652480,1sleep341-21ksoftirqd/312:36:583
24902470,0sleep02478-21sshd12:26:530
214512470,0sleep30-21swapper/311:40:433
154502470,0sleep00-21swapper/011:43:050
107532470,0sleep10-21swapper/109:56:311
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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