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2024-11-22 - 10:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack1slot8.osadl.org (updated Fri Nov 22, 2024 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
263309918171750,50cyclictest0-21swapper/019:10:030
2633099884803,53cyclictest0-21swapper/019:21:390
2633199823740,50cyclictest0-21swapper/119:21:381
258862719695,16sleep00-21swapper/019:05:570
26331995674,546cyclictest0-21swapper/119:10:021
2168991120,4rtkit-daemon2167-21rtkit-daemon00:09:081
2168991110,4rtkit-daemon2167-21rtkit-daemon00:18:431
2168991100,4rtkit-daemon2167-21rtkit-daemon22:26:361
2168991100,4rtkit-daemon2167-21rtkit-daemon20:28:101
2168991090,4rtkit-daemon2167-21rtkit-daemon00:22:391
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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