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2024-11-25 - 15:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack1slot3.osadl.org (updated Mon Nov 25, 2024 12:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2178235991413,0cyclictest0-21swapper/311:46:333
217823599140,13cyclictest0-21swapper/307:55:143
2178235991313,0cyclictest0-21swapper/312:39:483
2178235991313,0cyclictest0-21swapper/310:54:203
2178235991313,0cyclictest0-21swapper/310:25:393
2178235991313,0cyclictest0-21swapper/310:20:333
2178235991313,0cyclictest0-21swapper/310:14:243
2178235991313,0cyclictest0-21swapper/309:38:333
2178235991312,0cyclictest0-21swapper/310:55:123
2178235991312,0cyclictest0-21swapper/310:45:063
2178235991312,0cyclictest0-21swapper/310:36:563
2178235991312,0cyclictest0-21swapper/309:13:583
2178235991312,0cyclictest0-21swapper/309:07:493
217823599130,2cyclictest0-21swapper/308:45:123
220188821212,0sleep1542-21hwrng08:08:261
2178235991212,0cyclictest0-21swapper/312:27:323
2178235991212,0cyclictest0-21swapper/312:16:153
2178235991212,0cyclictest0-21swapper/312:13:113
2178235991212,0cyclictest0-21swapper/311:59:533
2178235991212,0cyclictest0-21swapper/311:53:433
2178235991212,0cyclictest0-21swapper/311:34:173
2178235991212,0cyclictest0-21swapper/311:21:583
2178235991212,0cyclictest0-21swapper/311:15:513
2178235991212,0cyclictest0-21swapper/310:18:293
2178235991212,0cyclictest0-21swapper/310:02:063
2178235991212,0cyclictest0-21swapper/309:31:243
2178235991212,0cyclictest0-21swapper/309:03:453
2178235991212,0cyclictest0-21swapper/308:56:343
2178235991212,0cyclictest0-21swapper/308:30:583
2178235991212,0cyclictest0-21swapper/308:27:533
2178235991212,0cyclictest0-21swapper/308:02:173
2178235991212,0cyclictest0-21swapper/307:39:453
2178235991211,0cyclictest0-21swapper/311:37:203
2178235991211,0cyclictest0-21swapper/311:05:123
2178235991211,0cyclictest0-21swapper/308:05:223
2178235991211,0cyclictest0-21swapper/307:11:053
217823599120,11cyclictest0-21swapper/309:41:453
2178235991111,0cyclictest0-21swapper/312:23:253
2178235991111,0cyclictest0-21swapper/312:09:053
2178235991111,0cyclictest0-21swapper/312:00:533
2178235991111,0cyclictest0-21swapper/311:00:283
2178235991111,0cyclictest0-21swapper/310:41:013
2178235991111,0cyclictest0-21swapper/310:34:523
2178235991111,0cyclictest0-21swapper/310:06:123
2178235991111,0cyclictest0-21swapper/309:20:073
2178235991111,0cyclictest0-21swapper/307:41:493
2178235991111,0cyclictest0-21swapper/307:26:283
2178235991111,0cyclictest0-21swapper/307:21:193
2178235991110,0cyclictest0-21swapper/311:12:453
2178235991110,0cyclictest0-21swapper/309:58:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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