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2025-04-02 - 08:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack1slot3.osadl.org (updated Wed Apr 02, 2025 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
205725799130,11cyclictest0-21swapper/319:55:123
205725799120,11cyclictest0-21swapper/323:55:193
205725799120,11cyclictest0-21swapper/321:55:013
205725799120,11cyclictest0-21swapper/321:35:003
2057257991111,0cyclictest0-21swapper/323:35:143
2057257991111,0cyclictest0-21swapper/319:54:563
2057257991110,0cyclictest0-21swapper/300:20:143
205725799110,8cyclictest0-21swapper/321:20:193
205725799110,10cyclictest0-21swapper/323:00:203
205725799110,10cyclictest0-21swapper/322:05:003
205725799110,10cyclictest0-21swapper/321:45:013
205725799110,10cyclictest0-21swapper/321:10:223
205725799110,10cyclictest0-21swapper/319:35:133
205725799110,0cyclictest0-21swapper/322:35:123
205725799110,0cyclictest0-21swapper/322:35:023
205725799110,0cyclictest0-21swapper/320:15:203
205725799110,0cyclictest0-21swapper/319:15:123
205725799110,0cyclictest0-21swapper/300:00:133
205725799109,0cyclictest0-21swapper/321:33:223
205725799109,0cyclictest0-21swapper/321:05:123
205725799109,0cyclictest0-21swapper/320:50:183
205725799108,1cyclictest0-21swapper/320:45:133
2057257991010,0cyclictest0-21swapper/323:10:153
2057257991010,0cyclictest0-21swapper/320:20:213
2057257991010,0cyclictest0-21swapper/320:00:183
2057257991010,0cyclictest0-21swapper/319:25:133
2057257991010,0cyclictest0-21swapper/319:20:193
2057257991010,0cyclictest0-21swapper/300:35:143
205725799100,9cyclictest0-21swapper/322:15:183
205725799100,0cyclictest0-21swapper/323:30:103
20572579999,0cyclictest0-21swapper/323:48:413
20572579999,0cyclictest0-21swapper/323:10:013
20572579999,0cyclictest0-21swapper/322:10:083
20572579999,0cyclictest0-21swapper/320:35:133
20572579999,0cyclictest0-21swapper/319:10:223
20572579999,0cyclictest0-21swapper/300:15:223
20572579998,0cyclictest0-21swapper/321:46:573
20572579990,0cyclictest0-21swapper/322:45:013
2055453291,5sleep30-21swapper/319:05:143
20572579988,0cyclictest0-21swapper/323:20:153
20572579980,0cyclictest0-21swapper/300:30:193
20572579977,0cyclictest0-21swapper/323:40:113
20572579977,0cyclictest0-21swapper/322:51:153
20572579977,0cyclictest0-21swapper/320:35:013
20572579977,0cyclictest0-21swapper/300:10:153
20572579977,0cyclictest0-21swapper/300:10:013
20572579970,6cyclictest0-21swapper/321:00:213
20572579966,0cyclictest0-21swapper/322:29:103
20572579966,0cyclictest0-21swapper/322:20:133
20572579966,0cyclictest0-21swapper/321:55:143
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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