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2024-11-22 - 10:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack1slot2.osadl.org (updated Fri Nov 22, 2024 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3068824028,0sleep30-21swapper/318:40:333
3069823825,0sleep00-21swapper/018:40:380
3052323627,0sleep20-21swapper/218:38:362
3042423526,0sleep10-21swapper/118:37:271
29925080,0irq/32-eth0-rx-22391-21kthreadcore20:47:123
8315070,0irq/26-0000:00:0-21swapper/319:11:543
329970,0watchdog/319646-21cut21:22:143
329970,0watchdog/30-21swapper/323:05:573
8315060,0irq/26-0000:00:0-21swapper/319:42:143
339960,0migration/327682-21sh22:06:553
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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