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2024-11-22 - 16:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot1.osadl.org (updated Fri Nov 22, 2024 12:45:18)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
235112210155,23sleep10-21swapper/107:08:111
234462210155,43sleep30-21swapper/307:07:203
235892206156,25sleep00-21swapper/007:09:090
235592203163,26sleep20-21swapper/207:08:472
2509421110,0sleep30-21swapper/310:00:143
254392930,0sleep30-21swapper/308:20:003
19722720,0sleep10-21swapper/109:30:161
295202580,0sleep10-21swapper/107:20:121
268102580,0sleep00-21swapper/012:03:380
217522160,0sleep10-21swapper/111:15:201
23747991412,1cyclictest28-21ksoftirqd/211:35:002
154762140,0sleep00-21swapper/011:50:010
306502130,0sleep30-21swapper/307:20:183
23747991311,1cyclictest28-21ksoftirqd/210:15:162
23747991211,1cyclictest28-21ksoftirqd/212:00:142
23747991210,1cyclictest28-21ksoftirqd/209:30:002
2374799119,1cyclictest28-21ksoftirqd/211:30:002
2374799119,1cyclictest28-21ksoftirqd/211:20:202
2374799119,1cyclictest28-21ksoftirqd/209:30:132
2374799119,1cyclictest28-21ksoftirqd/208:25:162
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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