You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2024-07-16 - 08:36
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack1slot1.osadl.org (updated Tue Jul 16, 2024 00:45:11)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
179762215160,25sleep00-21swapper/019:09:060
179682203162,27sleep20-21swapper/219:09:002
177292203165,25sleep10-21swapper/119:05:541
177562198161,23sleep30-21swapper/319:06:163
45232610,0sleep10-21swapper/123:16:261
77512530,0sleep10-21swapper/121:00:251
1815399250,24cyclictest0-21swapper/220:40:002
1815399140,13cyclictest21083-21apt-get22:10:132
1813599130,12cyclictest10838-21diskmemload22:00:310
188632110,0sleep310838-21diskmemload00:23:103
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional