You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-04-02 - 08:11
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack1slot1.osadl.org (updated Wed Apr 02, 2025 00:45:17)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
151662214149,23sleep00-21swapper/019:09:050
151272201165,22sleep10-21swapper/119:08:351
151732200161,26sleep20-21swapper/219:09:112
151292197160,24sleep30-21swapper/319:08:363
275562700,0sleep10-21swapper/123:55:181
34792150,0sleep20-21swapper/200:08:572
15343991515,0cyclictest35-21ksoftirqd/300:20:123
15336991515,0cyclictest28-21ksoftirqd/222:40:282
15343991414,0cyclictest0-21swapper/323:59:343
15336991412,1cyclictest28-21ksoftirqd/219:15:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional