You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-04-03 - 15:43

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Default latency plot of shadow in rack #0, slot #8

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
Special  All - All RT - Optimization - Ethernet - Thumbnails - Next
  
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot8s.osadl.org (updated Thu Apr 03, 2025 12:44:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
275991970,88ptp4l0-21swapper/107:05:071
222127055,12sleep70-21swapper/707:05:349
307826857,9sleep50-21swapper/507:08:447
143012680,1sleep6501rcuc/611:20:248
309726554,9sleep110-21swapper/1107:09:023
98626453,8sleep00-21swapper/007:05:270
186926452,9sleep40-21swapper/407:05:316
3230726354,7sleep60-21swapper/607:05:218
297525948,9sleep100-21swapper/1007:07:132
3585992812,2cyclictest0-21swapper/708:05:159
260532240,0chrt26055-21sed10:00:005
260532240,0chrt26055-21sed09:59:595
361199202,10cyclictest0-21swapper/1111:25:013
358199187,7cyclictest32626-21kworker/u24:111:00:018
358199183,9cyclictest0-21swapper/610:10:018
358199183,9cyclictest0-21swapper/610:10:008
275991180,2ptp4l21-21ksoftirqd/108:40:161
184122180,0sleep30-21swapper/308:10:005
361199171,2cyclictest0-21swapper/1111:10:133
358199173,8cyclictest0-21swapper/612:20:258
358199171,3cyclictest0-21swapper/610:15:188
355399173,9cyclictest0-21swapper/112:35:011
354999173,9cyclictest0-21swapper/009:24:590
354999173,8cyclictest0-21swapper/009:35:010
359899164,8cyclictest31456-21kworker/u24:009:10:0111
359899162,8cyclictest0-21swapper/910:50:0111
358199162,9cyclictest0-21swapper/609:15:008
357699163,8cyclictest0-21swapper/508:25:017
356299162,9cyclictest0-21swapper/307:30:005
354999163,8cyclictest0-21swapper/009:05:000
275991160,0ptp4l0-21swapper/111:40:231
207332160,0sleep10-21swapper/108:10:221
361199152,7cyclictest0-21swapper/1108:40:003
361199150,14cyclictest0-21swapper/1107:35:173
359899152,7cyclictest0-21swapper/909:30:0111
358599152,8cyclictest0-21swapper/710:15:019
358599152,7cyclictest0-21swapper/707:30:309
355399152,8cyclictest0-21swapper/108:30:011
355399151,8cyclictest0-21swapper/109:20:011
355399150,3cyclictest0-21swapper/108:05:151
354999153,8cyclictest0-21swapper/011:55:010
354999152,9cyclictest0-21swapper/007:40:000
354999152,8cyclictest0-21swapper/008:50:000
354999151,9cyclictest0-21swapper/009:25:010
361199142,7cyclictest0-21swapper/1108:50:003
359899142,7cyclictest0-21swapper/910:30:0111
359899141,10cyclictest31456-21kworker/u24:007:14:5911
358599141,7cyclictest0-21swapper/711:10:019
358199143,7cyclictest0-21swapper/612:30:018
358199141,8cyclictest0-21swapper/610:45:018
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional