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2024-11-22 - 11:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot8.osadl.org (updated Thu Nov 21, 2024 12:46:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7142549947325,30cyclictest0-21swapper/711:24:5513
71425799462460,1cyclictest2430412-21TaskCon~ller15
7142549946031,428cyclictest7912-21firefox09:54:5513
7142549944721,30cyclictest0-21swapper/709:24:5513
7142489944619,423cyclictest7940-21IPC1
7142619944012,30cyclictest0-21swapper/1308:09:265
7142579943913,29cyclictest0-21swapper/912:27:4515
714261994297,30cyclictest0-21swapper/1307:45:405
714248994260,29cyclictest0-21swapper/110:03:241
7142529942526,394cyclictest4109357-21Isolated21:43:2011
7142489942516,406cyclictest0-21swapper/107:57:431
7142489942418,404cyclictest0-21swapper/110:09:441
7142489942221,398cyclictest0-21swapper/109:07:511
7142489942220,398cyclictest0-21swapper/109:32:421
7142489942220,398cyclictest0-21swapper/109:32:421
7142489942120,398cyclictest0-21swapper/110:13:451
7142489942117,401cyclictest0-21swapper/111:27:351
714248994210,417cyclictest736176-21meminfo07:30:211
71425299420418,1cyclictest1150598-21IPC11
7142489942020,398cyclictest0-21swapper/111:05:441
7142489942020,0cyclictest0-21swapper/109:39:451
7142489942020,0cyclictest0-21swapper/109:39:451
7142489942018,400cyclictest0-21swapper/110:48:231
7142489941822,394cyclictest0-21swapper/108:28:451
7142489941742,374cyclictest2617867-21Isolated21:43:201
7142489941717,398cyclictest0-21swapper/111:17:341
7142579941618,397cyclictest0-21swapper/909:38:4515
7142579941618,397cyclictest0-21swapper/909:38:4515
7142489941618,396cyclictest0-21swapper/107:19:341
7142489941616,397cyclictest0-21swapper/108:38:451
7142489941516,397cyclictest0-21swapper/111:34:211
7142489941516,396cyclictest0-21swapper/110:28:211
7142489941514,398cyclictest0-21swapper/109:13:461
7142489941423,390cyclictest0-21swapper/110:31:421
7142489941313,398cyclictest0-21swapper/112:05:431
7142489941313,398cyclictest0-21swapper/112:05:431
714249994100,409cyclictest0-21swapper/207:52:358
714263994090,13cyclictest0-21swapper/1508:24:457
7142579940712,394cyclictest0-21swapper/909:23:4415
71425099407403,3cyclictest800011-21kworker/3:2+i915-unordered08:42:429
714257994055,397cyclictest0-21swapper/909:46:4815
7142579940516,388cyclictest0-21swapper/909:18:5915
714247994050,0cyclictest0-21swapper/011:13:330
714247994050,0cyclictest0-21swapper/010:26:460
714247994050,0cyclictest0-21swapper/008:12:470
7142579940311,0cyclictest0-21swapper/912:12:5915
7142579940311,0cyclictest0-21swapper/912:12:5915
71425999402401,1cyclictest0-21swapper/1108:42:423
7142489940114,386cyclictest0-21swapper/109:16:591
714252994008,391cyclictest0-21swapper/511:33:3511
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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