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2025-04-02 - 08:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot8.osadl.org (updated Tue Apr 01, 2025 12:46:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
68304099890,88cyclictest690975-21meminfo07:15:218
68304399870,86cyclictest735948-21meminfo08:05:2311
68304799850,84cyclictest843367-21meminfo10:20:2015
68304399830,82cyclictest931338-21meminfo12:20:2511
68305099820,81cyclictest700229-21meminfo07:25:224
68305099800,79cyclictest814316-21meminfo09:40:204
68304399800,79cyclictest790711-21meminfo09:10:1711
68304999770,76cyclictest753883-21meminfo08:25:203
68303899770,76cyclictest709152-21meminfo07:35:231
68304799760,75cyclictest819745-21meminfo09:50:1715
68303899740,73cyclictest819744-21meminfo09:50:161
68304999730,72cyclictest758488-21meminfo08:30:243
68304899720,71cyclictest722121-21meminfo07:50:252
68304199720,71cyclictest780661-21meminfo08:55:199
68305199710,70cyclictest775782-21meminfo08:50:235
68304299710,70cyclictest767139-21meminfo08:40:2410
68304299710,70cyclictest767139-21meminfo08:40:2410
68304199710,70cyclictest887345-21meminfo11:20:219
68305199690,68cyclictest735947-21meminfo08:05:225
68304699690,68cyclictest912570-21meminfo11:55:1714
68304699690,68cyclictest863737-21meminfo10:50:3514
68304499690,68cyclictest858287-21meminfo10:40:2112
68304299690,68cyclictest748998-21meminfo08:20:2010
68303799690,68cyclictest849628-21meminfo10:30:150
68304899680,67cyclictest907679-21meminfo11:50:152
68304899680,67cyclictest771454-21meminfo08:45:222
68304899680,67cyclictest771454-21meminfo08:45:222
68304799680,67cyclictest922625-21meminfo12:10:2215
68304799680,67cyclictest868606-21meminfo10:55:2115
68304799680,67cyclictest709151-21meminfo07:35:2115
68304299680,67cyclictest882981-21meminfo11:15:2110
68304299680,67cyclictest775781-21meminfo08:50:2310
68304299680,67cyclictest695344-21meminfo07:20:2210
68304199680,67cyclictest805666-21meminfo09:30:169
68304199680,67cyclictest731606-21meminfo08:00:229
68305199670,66cyclictest767140-21meminfo08:40:245
68305199670,66cyclictest767140-21meminfo08:40:245
68305199670,66cyclictest700227-21meminfo07:25:225
68304899670,66cyclictest926966-21meminfo12:15:212
68304899670,66cyclictest839005-21meminfo10:15:212
68304899670,66cyclictest727006-21meminfo07:55:232
68304499670,66cyclictest912572-21meminfo11:55:1812
68304199670,66cyclictest722120-21meminfo07:50:249
68303899670,66cyclictest922624-21meminfo12:10:221
68303899670,66cyclictest780660-21meminfo08:55:191
68303799670,66cyclictest685524-21meminfo07:10:230
68305199660,65cyclictest704841-21meminfo07:30:295
68304999660,65cyclictest878649-21meminfo11:10:173
68304999660,65cyclictest878649-21meminfo11:10:173
68304999660,65cyclictest809994-21meminfo09:35:213
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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