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2025-04-05 - 23:38

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #7

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot7s.osadl.org (updated Sat Apr 05, 2025 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
144634212672,22sleep20-21swapper/219:05:092
146204211871,20sleep30-21swapper/319:07:513
146124211771,38sleep00-21swapper/019:06:470
146040211370,32sleep10-21swapper/119:05:441
146518992919,4cyclictest138287-21kworker/0:1+kacpid19:20:520
14652099260,25cyclictest0-21swapper/121:47:311
14652099260,25cyclictest0-21swapper/119:36:051
14651899260,26cyclictest0-21swapper/021:41:180
14652399250,25cyclictest0-21swapper/219:15:152
14652099250,24cyclictest0-21swapper/119:27:461
14651899250,25cyclictest0-21swapper/019:15:480
14652099245,13cyclictest0-21swapper/123:08:331
146520992315,8cyclictest0-21swapper/120:05:561
14652399228,13cyclictest0-21swapper/223:08:492
14652599217,13cyclictest0-21swapper/320:24:093
146520992111,10cyclictest0-21swapper/120:40:161
14652099201,19cyclictest0-21swapper/120:56:261
14651899204,7cyclictest0-21swapper/023:26:160
14652599199,4cyclictest0-21swapper/323:16:573
14652599199,4cyclictest0-21swapper/323:16:573
14652399191,5cyclictest0-21swapper/220:05:142
146523991913,5cyclictest1051-21snmpd23:50:102
14652099190,1cyclictest0-21swapper/121:52:301
146518991910,0cyclictest0-21swapper/021:03:370
14652599189,4cyclictest0-21swapper/322:42:023
14652399189,4cyclictest0-21swapper/219:28:042
146523991813,4cyclictest1051-21snmpd22:28:352
14652399180,17cyclictest0-21swapper/221:48:582
14652099187,5cyclictest0-21swapper/100:34:361
14652099180,8cyclictest0-21swapper/121:33:231
14651899187,5cyclictest0-21swapper/021:15:020
14652599170,17cyclictest0-21swapper/321:21:353
14652599170,16cyclictest0-21swapper/319:51:253
14652599170,16cyclictest0-21swapper/319:37:403
146523991712,5cyclictest0-21swapper/221:40:142
14652399170,1cyclictest0-21swapper/222:15:172
14652099177,1cyclictest0-21swapper/122:28:411
14652099176,1cyclictest0-21swapper/121:12:171
14652099176,1cyclictest0-21swapper/100:29:121
14652099170,16cyclictest0-21swapper/123:20:141
14651899173,13cyclictest0-21swapper/022:55:150
14651899170,17cyclictest0-21swapper/022:46:530
14651899170,17cyclictest0-21swapper/021:33:470
14651899170,16cyclictest0-21swapper/000:07:080
146525991614,1cyclictest1051-21snmpd22:10:113
146525991612,4cyclictest0-21swapper/300:37:153
14652599160,7cyclictest0-21swapper/323:26:073
14652599160,7cyclictest0-21swapper/322:52:303
14652599160,7cyclictest0-21swapper/300:20:343
14652599160,16cyclictest0-21swapper/319:10:243
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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