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2025-04-02 - 08:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot7.osadl.org (updated Wed Apr 02, 2025 00:46:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
280503299417416,1cyclictest0-21swapper/222:23:598
2805080994160,415cyclictest0-21swapper/1422:23:596
280503299414414,0cyclictest0-21swapper/222:10:418
280502799414411,3cyclictest0-21swapper/023:55:450
280502799414411,3cyclictest0-21swapper/023:55:450
280502799414411,3cyclictest0-21swapper/020:39:350
280502799413410,3cyclictest0-21swapper/022:42:340
280506299408408,0cyclictest0-21swapper/922:10:4115
280508099407407,0cyclictest0-21swapper/1423:55:456
280508099407407,0cyclictest0-21swapper/1423:55:456
280508099407407,0cyclictest0-21swapper/1422:42:346
280508099407407,0cyclictest0-21swapper/1420:39:356
280507299402402,0cyclictest0-21swapper/1220:45:504
280507299402402,0cyclictest0-21swapper/1220:45:494
280504299387323,2cyclictest3074595-21kworker/u64:4+i915-dp@
i915_digport_work_func
02:48:2110
280504299387323,2cyclictest3074595-21kworker/u64:4+i915-dp@
i915_digport_work_func
00:17:2710
280506599386385,1cyclictest26150irq/128-ahci[0000:00:17.0]22:23:582
280506599384383,1cyclictest26150irq/128-ahci[0000:00:17.0]22:10:422
280504299348347,1cyclictest0-21swapper/422:02:2710
280504299347347,0cyclictest0-21swapper/423:03:5610
280504299347346,1cyclictest631rcuc/423:10:0710
280504299346346,0cyclictest0-21swapper/423:36:5910
280508299342342,0cyclictest0-21swapper/1523:55:467
280508299342342,0cyclictest0-21swapper/1523:55:457
280508299342342,0cyclictest0-21swapper/1522:42:347
280508299342342,0cyclictest0-21swapper/1520:39:357
280502999329263,1cyclictest3338485-21kworker/u64:4+events_unbound@
intel_display_power_put_async_work
22:10:421
280506999324323,1cyclictest0-21swapper/1120:45:493
280506999324323,1cyclictest0-21swapper/1120:45:493
280507299296226,1cyclictest3430983-21kworker/u64:0+events_unbound@
intel_display_power_put_async_work
23:10:074
280507299293226,1cyclictest3599736-21kworker/u64:3+events_unbound@
intel_display_power_put_async_work
23:36:594
280505899293227,1cyclictest3619923-21kworker/u64:1+events_unbound@
intel_display_power_put_async_work
23:55:4614
280505899293227,1cyclictest3619923-21kworker/u64:1+events_unbound@
intel_display_power_put_async_work
23:55:4514
2805027992880,287cyclictest0-21swapper/023:01:530
280507599287282,5cyclictest836399-21Renderer23:17:245
280507599287282,5cyclictest836399-21Renderer23:17:235
280502799287282,4cyclictest769900-21Xorg22:16:120
280506299286282,4cyclictest769900-21Xorg23:08:1715
280505899286283,1cyclictest0-21swapper/823:49:2414
280505899286281,4cyclictest838542-21Renderer20:37:3014
2805047992860,285cyclictest0-21swapper/523:44:4911
2805037992860,285cyclictest0-21swapper/322:14:019
2805032992860,283cyclictest0-21swapper/223:28:198
2805029992860,285cyclictest0-21swapper/123:11:581
280502799286282,4cyclictest838542-21Renderer23:20:320
280502799286281,5cyclictest838542-21Renderer22:25:590
280502799286281,5cyclictest838542-21Renderer22:21:010
2805080992852,282cyclictest0-21swapper/1422:13:236
280506999285280,5cyclictest769900-21Xorg22:19:323
280505899285281,3cyclictest769900-21Xorg23:50:5214
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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