You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2024-11-22 - 11:19
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot7.osadl.org (updated Fri Nov 22, 2024 00:46:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
183991499608424,124cyclictest2664391-21kworker/u64:3+events_unbound@
intel_display_power_put_async_work
23:27:510
18399319947511,59cyclictest0-21swapper/1023:16:262
18399329945625,29cyclictest0-21swapper/1100:03:453
18399339945224,29cyclictest0-21swapper/1222:37:304
18399329944918,29cyclictest0-21swapper/1123:33:363
18399229944925,30cyclictest0-21swapper/400:36:5910
18399329944818,29cyclictest0-21swapper/1123:57:323
183992899448385,2cyclictest2489980-21kworker/u64:2+events_unbound@
intel_display_power_put_async_work
22:26:2313
18399359944721,30cyclictest0-21swapper/1423:06:516
18399229944514,30cyclictest0-21swapper/422:26:4610
1839936994440,20cyclictest0-21swapper/1500:36:147
18399229944416,29cyclictest0-21swapper/423:52:2010
18399229944416,29cyclictest0-21swapper/423:52:1910
18399369944218,30cyclictest0-21swapper/1523:53:417
18399369944218,30cyclictest0-21swapper/1523:53:417
18399229944013,30cyclictest0-21swapper/422:40:4310
18399329943918,30cyclictest0-21swapper/1123:43:523
18399329943913,29cyclictest40810-21thunderbird22:06:243
1839922994399,30cyclictest0-21swapper/423:02:3410
18399229943710,29cyclictest0-21swapper/423:56:5010
1839918994369,30cyclictest0-21swapper/323:47:529
1839922994347,29cyclictest0-21swapper/400:33:5410
1839922994347,29cyclictest0-21swapper/400:33:5310
1839922994336,29cyclictest0-21swapper/422:11:3110
1839918994291,30cyclictest0-21swapper/322:44:509
1839929994255,29cyclictest0-21swapper/823:28:3314
18399189942524,400cyclictest0-21swapper/323:39:529
1839918994250,30cyclictest0-21swapper/322:59:269
1839929994240,30cyclictest0-21swapper/822:33:3314
1839929994231,30cyclictest0-21swapper/822:41:3214
1839935994220,24cyclictest0-21swapper/1423:16:506
183993399422421,1cyclictest0-21swapper/1223:09:484
1839929994223,30cyclictest0-21swapper/822:04:2314
1839929994222,30cyclictest0-21swapper/800:38:3814
1839935994190,419cyclictest0-21swapper/1423:41:376
1839935994190,419cyclictest0-21swapper/1422:54:266
1839935994190,22cyclictest0-21swapper/1423:36:366
1839935994190,21cyclictest0-21swapper/1422:32:326
1839935994190,20cyclictest0-21swapper/1422:02:346
1839935994180,21cyclictest0-21swapper/1423:56:266
1839935994180,21cyclictest0-21swapper/1423:52:426
1839935994180,21cyclictest0-21swapper/1423:52:416
1839935994180,21cyclictest0-21swapper/1423:46:456
1839935994180,21cyclictest0-21swapper/1422:59:486
1839935994180,20cyclictest0-21swapper/1422:43:296
1839935994180,20cyclictest0-21swapper/1422:21:466
1839935994180,20cyclictest0-21swapper/1422:09:306
1839935994170,417cyclictest0-21swapper/1422:12:336
1839935994170,417cyclictest0-21swapper/1400:04:316
18399189941722,394cyclictest0-21swapper/322:13:359
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional