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2025-04-02 - 04:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot7.osadl.org (updated Wed Apr 02, 2025 00:46:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
280503299417416,1cyclictest0-21swapper/222:23:598
2805080994160,415cyclictest0-21swapper/1422:23:596
280503299414414,0cyclictest0-21swapper/222:10:418
280502799414411,3cyclictest0-21swapper/023:55:450
280502799414411,3cyclictest0-21swapper/023:55:450
280502799414411,3cyclictest0-21swapper/020:39:350
280502799413410,3cyclictest0-21swapper/022:42:340
280506299408408,0cyclictest0-21swapper/922:10:4115
280508099407407,0cyclictest0-21swapper/1423:55:456
280508099407407,0cyclictest0-21swapper/1423:55:456
280508099407407,0cyclictest0-21swapper/1422:42:346
280508099407407,0cyclictest0-21swapper/1420:39:356
280507299402402,0cyclictest0-21swapper/1220:45:504
280507299402402,0cyclictest0-21swapper/1220:45:494
280504299387323,2cyclictest3074595-21kworker/u64:4+i915-dp@
i915_digport_work_func
02:48:2110
280504299387323,2cyclictest3074595-21kworker/u64:4+i915-dp@
i915_digport_work_func
00:17:2710
280506599386385,1cyclictest26150irq/128-ahci[0000:00:17.0]22:23:582
280506599384383,1cyclictest26150irq/128-ahci[0000:00:17.0]22:10:422
280504299348347,1cyclictest0-21swapper/422:02:2710
280504299347347,0cyclictest0-21swapper/423:03:5610
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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