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2024-11-22 - 10:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot7.osadl.org (updated Fri Nov 22, 2024 00:46:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
183991499608424,124cyclictest2664391-21kworker/u64:3+events_unbound@
intel_display_power_put_async_work
23:27:510
18399319947511,59cyclictest0-21swapper/1023:16:262
18399329945625,29cyclictest0-21swapper/1100:03:453
18399339945224,29cyclictest0-21swapper/1222:37:304
18399329944918,29cyclictest0-21swapper/1123:33:363
18399229944925,30cyclictest0-21swapper/400:36:5910
18399329944818,29cyclictest0-21swapper/1123:57:323
183992899448385,2cyclictest2489980-21kworker/u64:2+events_unbound@
intel_display_power_put_async_work
22:26:2313
18399359944721,30cyclictest0-21swapper/1423:06:516
18399229944514,30cyclictest0-21swapper/422:26:4610
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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