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2024-11-22 - 06:15

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #6

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot6s.osadl.org (updated Fri Nov 22, 2024 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
5041852311301,3sleep70-21swapper/719:06:4417
5043792307300,5sleep60-21swapper/619:09:2316
5043402306299,4sleep160-21swapper/1619:08:538
5041562304297,5sleep20-21swapper/219:06:1912
5043702303298,3sleep180-21swapper/1819:09:1510
5042402302297,3sleep100-21swapper/1019:07:272
5043922299292,5sleep170-21swapper/1719:09:349
5043892299292,5sleep140-21swapper/1419:09:316
5043862299292,4sleep120-21swapper/1219:09:294
5043742299292,5sleep10-21swapper/119:09:181
5043372297290,4sleep130-21swapper/1319:08:505
5043732295288,5sleep00-21swapper/019:09:170
5043992294288,4sleep30-21swapper/319:09:4013
5043432294286,5sleep190-21swapper/1919:08:5611
5043302294287,4sleep80-21swapper/819:08:4518
5041592294287,5sleep50-21swapper/519:06:2215
5043852293286,5sleep110-21swapper/1119:09:283
5043102292285,4sleep90-21swapper/919:08:2619
5043672291284,5sleep150-21swapper/1519:09:127
5043052289281,5sleep40-21swapper/419:08:2114
504807995252,0cyclictest0-21swapper/1722:49:219
50478299520,51cyclictest0-21swapper/1023:32:052
504780995252,0cyclictest0-21swapper/919:25:2719
50478099510,21cyclictest0-21swapper/900:37:3019
50475899510,51cyclictest0-21swapper/222:31:4912
504754995151,0cyclictest0-21swapper/119:19:101
50480199500,49cyclictest0-21swapper/1519:58:267
50480199500,49cyclictest0-21swapper/1519:58:267
504803994948,1cyclictest0-21swapper/1622:49:218
50479199490,49cyclictest0-21swapper/1323:19:065
50477199496,29cyclictest0-21swapper/621:55:2816
504754994917,31cyclictest0-21swapper/100:10:221
504754994917,31cyclictest0-21swapper/100:10:221
504754994916,32cyclictest0-21swapper/100:26:281
504791994817,30cyclictest0-21swapper/1300:38:075
504812994714,32cyclictest0-21swapper/1919:49:2411
504812994714,32cyclictest0-21swapper/1919:49:2411
504807994746,0cyclictest0-21swapper/1719:58:269
504807994746,0cyclictest0-21swapper/1719:58:269
504803994717,29cyclictest0-21swapper/1620:39:248
504782994716,31cyclictest0-21swapper/1021:24:072
504761994716,0cyclictest0-21swapper/320:20:3113
504754994616,30cyclictest0-21swapper/100:08:551
504754994616,30cyclictest0-21swapper/100:08:551
504791994514,31cyclictest0-21swapper/1323:34:465
504782994545,0cyclictest0-21swapper/1020:21:022
504782994545,0cyclictest0-21swapper/1019:25:272
504761994545,0cyclictest0-21swapper/319:25:2713
504761994514,1cyclictest0-21swapper/300:37:3013
504776994444,0cyclictest0-21swapper/821:26:4318
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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