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2025-04-02 - 08:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot6.osadl.org (updated Fri Feb 28, 2025 00:46:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
5669499953436,498cyclictest0-21swapper/721:50:4413
5669309953015,45cyclictest0-21swapper/221:28:568
5669309953015,45cyclictest0-21swapper/221:28:568
5669699952498,425cyclictest778100-21kworker/12:1+i915-unordered00:14:234
5669359952324,498cyclictest0-21swapper/319:40:209
5669809952021,499cyclictest0-21swapper/1522:21:237
5669309951921,498cyclictest0-21swapper/221:36:448
5669459951515,499cyclictest0-21swapper/620:46:4312
566969995125,506cyclictest0-21swapper/1221:57:214
5669809951115,496cyclictest0-21swapper/1519:35:217
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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