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2025-04-02 - 08:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot5.osadl.org (updated Tue Apr 01, 2025 00:43:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
392439199624624,0cyclictest0-21swapper/720:20:5813
392437899613613,0cyclictest0-21swapper/320:07:589
392437899613613,0cyclictest0-21swapper/320:07:589
392439199608608,0cyclictest0-21swapper/720:48:4213
392439199602602,0cyclictest0-21swapper/722:20:5813
39244059960037,44cyclictest0-21swapper/1019:44:422
392437199591296,294cyclictest0-21swapper/119:16:421
392441899589589,0cyclictest0-21swapper/1423:55:586
392439199587587,0cyclictest0-21swapper/700:38:4413
392439199585585,0cyclictest0-21swapper/721:46:2113
392441299576576,0cyclictest0-21swapper/1223:26:584
392441299576576,0cyclictest0-21swapper/1223:26:584
392441299574573,1cyclictest0-21swapper/1220:19:434
392437699564564,0cyclictest0-21swapper/219:41:448
39244059956040,519cyclictest0-21swapper/1019:50:202
392440599559559,0cyclictest0-21swapper/1022:40:222
392441899558558,0cyclictest0-21swapper/1423:25:216
392441899558558,0cyclictest0-21swapper/1423:25:216
39243919954542,502cyclictest0-21swapper/723:53:4213
39243919954541,503cyclictest0-21swapper/721:00:5813
39243919954535,505cyclictest0-21swapper/720:10:2113
39243889954120,521cyclictest0-21swapper/620:03:4212
39243889954120,521cyclictest0-21swapper/620:03:4212
39243819953414,519cyclictest0-21swapper/420:17:2110
39243919953328,504cyclictest0-21swapper/722:10:5813
39243689953320,512cyclictest0-21swapper/022:23:440
39244059953119,512cyclictest0-21swapper/1022:45:582
3924405995290,529cyclictest114-21ksoftirqd/1022:37:582
39244129952820,507cyclictest0-21swapper/1223:43:434
39244129952820,507cyclictest0-21swapper/1223:43:434
39244059952815,512cyclictest0-21swapper/1019:34:582
39243919952377,444cyclictest4040310-21kworker/7:1+i915-unordered21:42:2113
39243869952243,477cyclictest0-21swapper/520:20:2111
39244129952114,506cyclictest0-21swapper/1220:42:584
3924388995216,25cyclictest0-21swapper/600:08:1912
39243789952016,503cyclictest0-21swapper/322:57:439
3924412995190,518cyclictest0-21swapper/1221:41:204
3924405995179,57cyclictest0-21swapper/1021:03:412
39243919951744,473cyclictest0-21swapper/700:08:4113
39243919951641,473cyclictest0-21swapper/721:33:4213
39243919951639,474cyclictest0-21swapper/723:14:2213
392441599515515,0cyclictest0-21swapper/1300:24:585
39243919951541,473cyclictest0-21swapper/723:07:2013
39243919951541,473cyclictest0-21swapper/720:43:4613
3924409995142,24cyclictest0-21swapper/1119:11:583
39243919951439,474cyclictest0-21swapper/723:26:4413
39243919951439,474cyclictest0-21swapper/723:26:4413
39243919951439,474cyclictest0-21swapper/720:04:4413
39243919951439,474cyclictest0-21swapper/720:04:4413
39243919951423,28cyclictest0-21swapper/700:21:4113
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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