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2024-11-25 - 07:08

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot4s.osadl.org (updated Mon Nov 25, 2024 00:46:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
37851582381356,15sleep140-21swapper/1419:09:496
37848572368322,14sleep60-21swapper/619:05:5512
37849692367321,14sleep40-21swapper/419:07:1210
37851722351329,13sleep90-21swapper/919:09:5915
37849592351343,5sleep110-21swapper/1119:07:043
37851332350326,14sleep80-21swapper/819:09:2614
37851542348325,14sleep100-21swapper/1019:09:442
37851262348326,14sleep10-21swapper/119:09:191
37850102348325,14sleep20-21swapper/219:07:448
37849632347322,15sleep150-21swapper/1519:07:087
37848682347323,14sleep00-21swapper/019:06:050
37849832346323,14sleep120-21swapper/1219:07:224
37848202346323,14sleep130-21swapper/1319:05:295
37850132343320,14sleep50-21swapper/519:07:4711
37849982342317,15sleep70-21swapper/719:07:3313
37849922341317,14sleep30-21swapper/319:07:299
3785598995147,4cyclictest0-21swapper/1120:01:283
3785598994943,6cyclictest0-21swapper/1122:50:253
3785598994844,4cyclictest3910896-21kworker/11:0-i915-unordered21:02:513
3785598994844,4cyclictest0-21swapper/1123:14:173
378559899460,44cyclictest0-21swapper/1121:50:173
378559899460,29cyclictest0-21swapper/1121:59:533
3785598994541,4cyclictest0-21swapper/1122:08:253
3785598994541,4cyclictest0-21swapper/1119:36:333
3785598994537,6cyclictest0-21swapper/1121:35:233
3785598994537,6cyclictest0-21swapper/1121:35:233
378559899450,41cyclictest0-21swapper/1120:46:113
3785598994440,0cyclictest0-21swapper/1122:30:273
378559099440,42cyclictest0-21swapper/800:18:5614
3785598994339,4cyclictest124-21ksoftirqd/1122:12:593
3785598994339,4cyclictest0-21swapper/1123:33:293
3785598994339,4cyclictest0-21swapper/1122:19:553
3785598994339,0cyclictest3732930-21kworker/11:2+mm_percpu_wq19:11:393
3785598994339,0cyclictest0-21swapper/1123:26:573
3785598994336,3cyclictest3572734-21kworker/11:0-mm_percpu_wq19:25:373
3785598994335,4cyclictest3803194-21kworker/11:1-mm_percpu_wq20:29:533
3785598994335,4cyclictest0-21swapper/1123:56:413
3785598994334,5cyclictest3958737-21kworker/u32:0+flush-259:021:05:293
3785592994342,0cyclictest0-21swapper/921:08:1715
3785598994238,4cyclictest0-21swapper/1119:24:093
3785598994238,0cyclictest0-21swapper/1123:20:013
3785598994238,0cyclictest0-21swapper/1121:40:173
3785598994238,0cyclictest0-21swapper/1100:06:423
3785598994238,0cyclictest0-21swapper/1100:01:363
3785598994236,4cyclictest0-21swapper/1122:03:313
3785598994236,2cyclictest0-21swapper/1123:46:253
3785598994222,16cyclictest0-21swapper/1121:12:413
378559899420,34cyclictest0-21swapper/1121:45:193
3785596994242,0cyclictest0-21swapper/1022:12:592
3785592994242,0cyclictest0-21swapper/920:42:4115
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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