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2024-07-16 - 15:39

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #2

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot2s.osadl.org (updated Tue Jul 16, 2024 12:44:11)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
125976899447446,1cyclictest1422906-21kworker/9:0+events12:37:539
125976899447446,1cyclictest1321080-21kworker/9:2+events09:11:459
125976899447446,1cyclictest1315703-21kworker/9:0+events09:29:259
125976899447445,2cyclictest1373524-21kworker/9:2+events10:51:509
125976899446445,1cyclictest1411184-21kworker/9:0+events11:52:519
125976899446445,1cyclictest1408495-21kworker/9:2+events12:08:179
125976899446445,1cyclictest1408495-21kworker/9:2+events11:46:499
125976899446445,1cyclictest1392625-21kworker/9:1+events11:42:189
125976899446445,1cyclictest1376706-21kworker/9:0+events11:01:049
125976899446445,1cyclictest1373524-21kworker/9:2+events11:09:529
125976899446445,1cyclictest1373524-21kworker/9:2+events10:46:149
125976899446445,1cyclictest1344955-21kworker/9:2+events10:31:589
125976899446445,1cyclictest1344955-21kworker/9:2+events09:51:159
125976899446445,1cyclictest1339565-21kworker/9:0+events09:43:489
125976899446445,1cyclictest1315703-21kworker/9:0+events09:22:339
125976899446445,1cyclictest1315703-21kworker/9:0+events09:03:499
125976899446445,1cyclictest1284108-21kworker/9:0+events08:03:189
125976899446445,1cyclictest1281427-21kworker/9:1+events07:57:529
125976899446445,1cyclictest1270732-21kworker/9:0+events07:41:499
125976899446445,1cyclictest1259221-21kworker/9:0+events07:15:329
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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