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2025-04-02 - 08:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Wed Apr 02, 2025 00:43:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
79322725747,7sleep60-21swapper/603:35:466
79345125343,7sleep50-21swapper/503:38:585
79324625320,29sleep70-21swapper/703:36:037
79329024939,7sleep40-21swapper/403:36:404
79378399390,37cyclictest944232-21latency_hist04:59:117
79378399350,33cyclictest643-21systemd-journal04:04:127
793776993230,2cyclictest1120768-21kworker/u16:1+events_unbound06:45:215
793771993230,2cyclictest1030046-21kworker/u16:5+flush-8:006:09:414
793776993129,2cyclictest1030046-21kworker/u16:5+events_unbound06:20:225
793771993129,2cyclictest1030046-21kworker/u16:5+events_unbound06:30:124
793776993028,2cyclictest943922-21kworker/u16:0+events_unbound07:54:205
793776993028,2cyclictest827650-21kworker/u16:4+events_unbound04:05:215
793776993028,2cyclictest1185268-21kworker/u16:1+events_unbound07:16:215
79378399290,27cyclictest1260973-21latency_hist08:04:107
793779992927,2cyclictest1234895-21kworker/u16:5+flush-8:008:29:296
793776992927,2cyclictest990482-21kworker/u16:2+events_unbound05:51:215
793779992826,2cyclictest1006765-21kworker/u16:3+events_unbound05:29:296
793776992826,2cyclictest1030046-21kworker/u16:5+events_unbound05:47:225
793783992724,1cyclictest0-21swapper/708:24:367
793779992725,2cyclictest990482-21kworker/u16:2+events_unbound06:04:266
793779992725,2cyclictest849726-21kworker/u16:0+events_unbound04:29:266
793779992724,2cyclictest1153312-21kworker/u16:2+events_unbound06:59:136
793776992725,2cyclictest990482-21kworker/u16:2+events_unbound06:10:365
793776992725,2cyclictest943922-21kworker/u16:0+events_unbound04:58:215
793776992725,2cyclictest779745-21kworker/u16:2+flush-8:003:49:225
793776992725,2cyclictest1304012-21kworker/u16:0+events_unbound09:09:095
793776992725,2cyclictest1304012-21kworker/u16:0+events_unbound08:37:205
793771992723,3cyclictest990482-21kworker/u16:2+flush-8:006:04:214
793779992624,2cyclictest827650-21kworker/u16:4+flush-8:004:24:376
793779992624,2cyclictest1132531-21kworker/u16:3+flush-8:007:59:336
793779992623,2cyclictest943922-21kworker/u16:0+events_unbound07:39:136
793776992624,2cyclictest827650-21kworker/u16:4+events_unbound04:11:375
793776992624,2cyclictest827650-21kworker/u16:4+events_unbound03:59:105
793776992624,2cyclictest1234895-21kworker/u16:5+events_unbound08:23:215
793771992624,2cyclictest943922-21kworker/u16:0+events_unbound07:12:214
793771992623,2cyclictest1234895-21kworker/u16:5+flush-8:008:29:214
793771992623,2cyclictest1153312-21kworker/u16:2+events_unbound08:36:214
793776992523,2cyclictest741476-21kworker/u16:3+events_unbound04:02:225
793776992523,2cyclictest1185268-21kworker/u16:1+events_unbound07:33:215
793776992523,2cyclictest1006765-21kworker/u16:3+events_unbound05:30:185
793771992523,2cyclictest990482-21kworker/u16:2+flush-8:006:14:224
793771992523,2cyclictest849726-21kworker/u16:0+flush-8:004:04:334
793776992422,2cyclictest943922-21kworker/u16:0+flush-8:005:04:455
793776992422,2cyclictest879870-21kworker/u16:5+flush-8:004:36:175
793776992422,2cyclictest870214-21kworker/u16:1+flush-8:004:21:375
793776992422,2cyclictest870214-21kworker/u16:1+flush-8:004:21:375
793776992422,2cyclictest1026719-21kworker/u16:4+events_unbound07:05:215
793776992421,2cyclictest1324950-21kworker/u16:4+events_unbound08:56:215
793771992422,2cyclictest990482-21kworker/u16:2+events_unbound05:50:574
793771992422,2cyclictest1132531-21kworker/u16:3+events_unbound07:06:214
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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