You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2024-07-16 - 08:38
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot2.osadl.org (updated Tue Jul 16, 2024 00:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
161087626352,6sleep70-21swapper/718:58:307
161087626352,6sleep70-21swapper/718:58:307
2679189500,30rtkit-daemon0-21swapper/418:59:444
2679189500,30rtkit-daemon0-21swapper/418:59:444
1620115994543,2cyclictest1906614-21kworker/u16:3+flush-8:022:13:554
1620116993937,2cyclictest1848767-21kworker/u16:4+flush-8:021:12:265
161958123525,7sleep50-21swapper/519:00:135
161958123525,7sleep50-21swapper/519:00:135
161956223221,8sleep60-21swapper/618:59:576
161956223221,8sleep60-21swapper/618:59:576
1620115993028,2cyclictest1956125-21kworker/u16:0+flush-8:022:33:324
1620115993028,2cyclictest1906614-21kworker/u16:3+events_unbound21:49:424
162011899250,23cyclictest0-21swapper/720:20:437
1620116992422,2cyclictest2054239-21kworker/u16:3+flush-8:022:58:335
1620116992422,2cyclictest1741564-21kworker/u16:1+events_unbound20:15:255
1620116992422,2cyclictest1721566-21kworker/u16:0+flush-8:020:03:115
1620115992420,3cyclictest1609756-21kworker/u16:2+events_unbound19:53:314
1620118992315,7cyclictest0-21swapper/720:31:557
1620116992321,2cyclictest1996085-21kworker/u16:1+events_unbound22:13:545
1620116992321,2cyclictest1848767-21kworker/u16:4+events_unbound21:03:595
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional