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2024-11-22 - 17:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot0.osadl.org (updated Fri Nov 22, 2024 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2857621580,0sleep40-21swapper/412:31:064
2857621580,0sleep40-21swapper/412:31:054
699221480,0sleep50-21swapper/510:50:005
2365021150,0sleep2311rcuc/210:38:102
538121140,0sleep70-21swapper/711:08:217
538121140,0sleep70-21swapper/711:08:217
356021140,0sleep70-21swapper/711:31:227
1964821140,0sleep00-21swapper/009:30:360
1964821140,0sleep00-21swapper/009:30:350
1150221100,0sleep70-21swapper/709:29:387
52121060,1sleep11037-21runrttasks11:35:321
3258521060,0sleep20-21swapper/212:13:012
3258521060,0sleep20-21swapper/212:13:012
413821050,0sleep30-21swapper/310:54:143
413821050,0sleep30-21swapper/310:54:143
2330121050,1sleep00-21swapper/011:38:590
276021040,0sleep60-21swapper/610:11:056
2995421010,0sleep30-21swapper/309:41:363
70952950,1sleep07087-21sshd11:03:570
288332950,0sleep40-21swapper/410:53:024
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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